Seagate Ultra 320 User Manuals

Table of Contents

• 1.0 Interface requirements 1

  7
  • 1.1 How to use this interface manual 1

    7
    • 1.1.1 Scope of SCSI standards 2

      7
    • 1.1.2 Applicable standards 3

      7
  • 1.2 General interface description 3

    7
    • 1.2.1 Glossary 4

      7
    • 1.2.2 Keywords 11

      7
  • 1.3 Physical interface characteristics 12

    7
  • 1.4 Summary of SCSI messages 12

    7
• 2.0 SCSI bus 13

  7
  • 2.1 SCSI bus signals overview 15

    7
    • 2.1.1 Drive select 17

      7
    • 2.1.2 Signal values 17

      7
  • 2.2 Signal states 17

    7
    • 2.2.1 SE signals 17

      7
    • 2.2.2 LVD signals 17

      7
  • 2.3 OR-tied signals 18

    7
  • 2.4 Signal sources 19

    7
  • 2.5 SCSI bus timing 20

    7
    • 2.5.1 Arbitration delay 26

      7
    • 2.5.2 ATN transmit setup time 26

      7
    • 2.5.3 ATN receive setup time 26

      7
    • 2.5.4 Bus clear delay 27

      7
    • 2.5.5 Bus free delay 27

      7
    • 2.5.6 Bus set delay 27

      7
    • 2.5.7 Bus settle delay 27

      7
    • 2.5.8 Cable skew delay 27

      7
    • 2.5.9 Chip noise in receiver 27

      7
    • 2.5.10 Clock jitter 27

      7
    • 2.5.11 Crosstalk time shift 27

      7
    • 2.5.12 De-skewed data valid window 28

      7
    • 2.5.13 Flow control receive hold time 28

      7
    • 2.5.14 Flow control receive setup time 28

      7
    • 2.5.15 Flow control transmit hold time 28

      7
    • 2.5.16 Flow control transmit setup time 28

      7
    • 2.5.17 pCRC receive hold time 28

      7
    • 2.5.18 pCRC receive setup time 28

      7
    • 2.5.19 pCRC transmit hold time 28

      7
    • 2.5.20 pCRC transmit setup time 28

      7
    • 2.5.21 Data release delay 29

      7
    • 2.5.22 DIFFSENS voltage filter time 29

      7
    • 2.5.23 Offset induced time asymmetry 29

      7
    • 2.5.24 Physical disconnection delay 29

      7
    • 2.5.25 Power on to selection 29

      7
    • 2.5.26 QAS arbitration delay 29

      7
    • 2.5.27 QAS assertion delay 29

      7
    • 2.5.28 QAS release delay 29

      7
    • 2.5.29 QAS non-data phase REQ(ACK) period 29

      7
    • 2.5.30 Receive assertion period 29

      7
    • 2.5.31 Receive hold time 29

      7
    • 2.5.32 Receive internal hold time 30

      7
    • 2.5.33 Receive internal setup time 30

      7
    • 2.5.34 Receive negation period 30

      7
    • 2.5.35 Receive setup time 30

      8
    • 2.5.36 Receive REQ(ACK) period tolerance 30

      8
    • 2.5.37 Receive REQ assertion period with P_CRCA transitioning 30

      8
    • 2.5.38 Receive REQ negation period with P_CRCA transitioning 30

      8
    • 2.5.39 Receive skew compensation 30

      8
    • 2.5.40 Receiver amplitude time skew 31

      8
    • 2.5.41 REQ(ACK) period 31

      8
    • 2.5.42 Reset delay 31

      8
    • 2.5.43 Reset hold time 31

      8
    • 2.5.44 Reset to selection 31

      8
    • 2.5.45 Residual skew error 31

      8
    • 2.5.46 Selection abort time 31

      8
    • 2.5.47 Selection timeout delay 31

      8
    • 2.5.48 Signal timing skew 31

      8
    • 2.5.49 Skew correction range 32

      8
    • 2.5.50 Strobe offset tolerance 32

      8
    • 2.5.51 System deskew delay 32

      8
    • 2.5.52 System noise at launch 32

      8
    • 2.5.53 System noise at receiver 32

      8
    • 2.5.54 Time asymmetry 32

      8
    • 2.5.55 Transmit assertion period 32

      8
    • 2.5.56 Transmit hold time 32

      8
    • 2.5.57 Transmit ISI compensation 32

      8
    • 2.5.58 Transmit negation period 32

      8
    • 2.5.59 Transmit setup time 33

      8
    • 2.5.60 Transmit REQ(ACK) period tolerance 33

      8
    • 2.5.61 Transmit REQ assertion period with P_CRCA transitioning 33

      8
    • 2.5.62 Transmit REQ negation period with P_CRCA transitioning 33

      8
    • 2.5.63 Transmitter skew 33

      8
    • 2.5.64 Transmitter time asymmetry 33

      8
  • 2.6 Measurement points 33

    8
    • 2.6.1 SE Fast-5 and Fast-10 measurement points 33

      8
    • 2.6.2 SE Fast-20 measurement points 33

      8
    • 2.6.3 LVD measurement points 34

      8
  • 2.7 Clocking methods for data transfers 34

    8
  • 2.8 Paced transfer on a SCSI bus 36

    8
  • 2.9 Data transfer modes 37

    8
    • 2.9.1 Asynchronous transfers 37

      8
    • 2.9.2 Synchronous transfers 37

      8
    • 2.9.3 Paced transfers 37

      8
  • 2.10 ST DATA phase parallel transfers 38

    8
  • 2.11 DT DATA phase parallel transfers 38

    8
    • 2.11.1 Data group transfers 38

      8
    • 2.11.2 Information unit transfers 38

      8
  • 2.12 Negotiation 39

    8
    • 2.12.1 Negotiation algorithm 39

      8
    • 2.12.2 When to negotiate 40

      8
    • 2.12.3 Negotiable fields 40

      8
    • 2.12.4 Transfer agreements 42

      8
    • 2.12.5 Transfer period factor 43

      8
    • 2.12.6 REQ/ACK offset 44

      8
    • 2.12.7 Transfer width exponent 44

      8
    • 2.12.8 Protocol options 45

      8
      • 2.12.8.1 IU_REQ 45

        8
      • 2.12.8.2 DT_REQ 46

        8
      • 2.12.8.3 QAS_REQ 46

        9
      • 2.12.8.4 HOLD_MCS 46

        9
      • 2.12.8.5 WR_FLOW 47

        9
      • 2.12.8.6 RD_STRM 47

        9
      • 2.12.8.7 RTI (Retain Training Information) 47

        9
      • 2.12.8.8 PCOMP_EN 47

        9
    • 2.12.9 Negotiable field combinations 48

      9
    • 2.12.10 Message restrictions 49

      9
    • 2.12.11 Negotiation message sequences 49

      9
• 3.0 Logical characteristics 51

  9
  • 3.1 SCSI bus phases overview 51

    9
    • 3.1.1 BUS FREE phase 51

      9
      • 3.1.1.1 Unexpected and expected bus free phases 51

        9
      • 3.1.1.2 Expected bus free phases 52

        9
    • 3.1.2 Arbitration and QAS overview 52

      9
      • 3.1.2.1 Normal ARBITRATION phase 53

        9
      • 3.1.2.2 QAS protocol 54

        9
      • 3.1.2.3 QAS phase overview 54

        9
  • 3.2 SELECTION phase 55

    9
    • 3.2.1 Selection overview 56

      9
      • 3.2.1.1 Selection using attention condition 56

        9
        • 3.2.1.1.1 Starting the SELECTION phase when using attention condition 56

          9
        • 3.2.1.1.2 Information unit transfers disabled 56

          9
        • 3.2.1.1.3 Information unit transfers enabled 56

          9
        • 3.2.1.1.4 Selection using attention condition timeout procedure 57

          9
      • 3.2.1.2 Selection without using attention condition 57

        9
        • 3.2.1.2.1 Information unit transfers disabled or enabled 57

          9
        • 3.2.1.2.2 Selection without using attention condition time-out procedure 57

          9
  • 3.3 RESELECTION phase 58

    9
    • 3.3.1 RESELECTION phase overview 58

      9
    • 3.3.2 Physical reconnection 58

      9
    • 3.3.3 Physical reconnection timeout procedure 59

      9
  • 3.4 SCSI bus fairness 59

    9
  • 3.5 Information transfer phases 60

    9
    • 3.5.1 Asynchronous transfer 61

      9
    • 3.5.2 Synchronous transfer 61

      9
      • 3.5.2.1 ST synchronous data transfer 61

        9
      • 3.5.2.2 DT synchronous transfer 62

        9
        • 3.5.2.2.1 Information unit transfer 62

          9
        • 3.5.2.2.2 Data group data field transfer 64

          9
    • 3.5.3 Paced transfer 68

      9
      • 3.5.3.1 Paced transfer training pattern 68

        9
        • 3.5.3.1.1 DT DATA IN phase training pattern 69

          9
        • 3.5.3.1.2 DT DATA OUT phase training pattern 70

          9
      • 3.5.3.2 P1 data valid/invalid state transitions 71

        9
        • 3.5.3.2.1 Starting pacing transfers at end of training pattern 72

          9
        • 3.5.3.2.2 Starting pacing transfers with no training pattern 72

          9
        • 3.5.3.2.3 Ending pacing transfers 73

          9
      • 3.5.3.3 Paced information unit transfer 73

        9
      • 3.5.3.4 Deskewing 74

        9
    • 3.5.4 Wide transfer 74

      9
  • 3.6 COMMAND phase 75

    9
    • 3.6.1 COMMAND phase description 75

      9
    • 3.6.2 COMMAND phase exception condition handling 75

      9
  • 3.7 DATA phase 75

    9
    • 3.7.1 DATA phase overview 75

      10
    • 3.7.2 DT DATA IN phase 75

      10
    • 3.7.3 DT DATA OUT phase 76

      10
    • 3.7.4 ST DATA IN phase 76

      10
    • 3.7.5 ST DATA OUT phase 76

      10
  • 3.8 STATUS phase 76

    10
    • 3.8.1 STATUS phase description 76

      10
    • 3.8.2 STATUS phase exception condition handling 76

      10
  • 3.9 MESSAGE phase 76

    10
    • 3.9.1 MESSAGE phase overview 76

      10
    • 3.9.2 MESSAGE IN phase 76

      10
      • 3.9.2.1 MESSAGE IN phase exception condition handling 77

        10
    • 3.9.3 MESSAGE OUT phase 77

      10
      • 3.9.3.1 MESSAGE OUT phase exception condition handling 77

        10
  • 3.10 Signal restrictions between phases 77

    10
  • 3.11 SCSI bus phase sequences 78

    10
    • 3.11.1 SCSI bus phase sequences overview 78

      10
    • 3.11.2 Phase sequences for physical reconnection and selection using attention condition with information unit transfers disabled 78

      10
    • 3.11.3 Phase sequences for selection without using attention condition with information unit transfers disabled 79

      10
    • 3.11.4 Phase sequences for physical reconnection or selection without using attention condition with information unit transfers enabled 80

      10
    • 3.11.5 Phase sequences for physical selection using attention condition with information unit transfers enabled 81

      10
  • 3.12 Data bus protection 81

    10
    • 3.12.1 Data bus protection overview 81

      10
    • 3.12.2 ST data bus protection using parity 81

      10
    • 3.12.3 DT data bus protection using CRC 82

      10
      • 3.12.3.1 DT data bus protection using CRC overview 82

        10
      • 3.12.3.2 Error detection capabilities 82

        10
      • 3.12.3.3 Order of bytes in the CRC field 82

        10
• 4.0 Message system specification 83

  10
  • 4.1 General message protocols and formats 83

    10
  • 4.2 Message formats 83

    10
    • 4.2.1 One-byte messages 84

      10
    • 4.2.2 Two-byte messages 84

      10
    • 4.2.3 Extended messages 84

      10
  • 4.3 Message categories 85

    10
    • 4.3.1 LINK CONTROL MESSAGES 85

      10
    • 4.3.2 DISCONNECT 87

      10
    • 4.3.3 IDENTIFY 87

      10
    • 4.3.4 IGNORE WIDE RESIDUE 88

      10
    • 4.3.5 INITIATOR DETECTED ERROR 89

      10
    • 4.3.6 LINKED COMMAND COMPLETE 89

      10
    • 4.3.7 MESSAGE PARITY ERROR 89

      10
    • 4.3.8 MESSAGE REJECT 89

      10
    • 4.3.9 MODIFY DATA POINTER 89

      10
    • 4.3.10 MODIFY BIDIRECTIONAL DATA POINTER 90

      10
    • 4.3.11 NO OPERATION 91

      10
    • 4.3.12 PARALLEL PROTOCOL REQUEST 92

      10
      • 4.3.12.1 PARALLEL PROTOCOL REQUEST 95

        10
    • 4.3.13 QAS REQUEST 96

      10
    • 4.3.14 RESTORE POINTERS 96

      10
    • 4.3.15 SAVE DATA POINTERS 96

      10
    • 4.3.16 SYNCHRONOUS DATA TRANSFER REQUEST 97

      11
      • 4.3.16.1 Target initiated SDTR negotiation 99

        11
      • 4.3.16.2 Initiator initiated SDTR negotiation 99

        11
    • 4.3.17 TASK COMPLETE 99

      11
    • 4.3.18 WIDE DATA TRANSFER REQUEST 100

      11
      • 4.3.18.1 Target initiated WDTR negotiation 101

        11
      • 4.3.18.2 Initiator initiated Wide Data Transfer Request (WDTR) negotiation 102

        11
  • 4.4 Task attribute messages 102

    11
    • 4.4.1 Task attribute message overview and codes 102

      11
    • 4.4.2 ACA (AUTO CONTINGENT ALLEGIANCE) 103

      11
    • 4.4.3 HEAD OF QUEUE 104

      11
    • 4.4.4 ORDERED 104

      11
    • 4.4.5 SIMPLE 104

      11
  • 4.5 Task management messages 105

    11
    • 4.5.1 Task management message codes 105

      11
    • 4.5.2 ABORT TASK 105

      11
    • 4.5.3 ABORT TASK SET 106

      11
    • 4.5.4 CLEAR ACA 106

      11
    • 4.5.5 CLEAR TASK SET 106

      11
    • 4.5.6 LOGICAL UNIT RESET 106

      11
    • 4.5.7 TARGET RESET 106

      11
• 5.0 Miscellaneous SCSI bus characteristics 107

  11
  • 5.1 Attention condition 107

    11
  • 5.2 Bus reset condition 108

    11
  • 5.3 Hard reset 108

    11
  • 5.4 Reset events 109

    11
    • 5.4.1 Bus reset event 109

      11
    • 5.4.2 Power on reset event 109

      11
    • 5.4.3 Target reset event 109

      11
    • 5.4.4 Transceiver mode change reset event 109

      11
  • 5.5 Asynchronous condition recovery 109

    11
    • 5.5.1 SCSI pointers 109

      11
    • 5.5.2 Active pointers 110

      11
    • 5.5.3 Saved pointers 110

      11
  • 5.6 Command processing considerations and exception conditions 111

    11
    • 5.6.1 Command processing considerations and exception conditions overview 111

      11
    • 5.6.2 Asynchronous event notification 111

      11
    • 5.6.3 Incorrect initiator connection 111

      11
    • 5.6.4 Unexpected RESELECTION phase 112

      11
• 6.0 SPI information units 113

  11
  • 6.1 Information unit transfer logical operations 113

    11
  • 6.2 SPI information units 118

    11
    • 6.2.1 SPI command information unit 118

      11
    • 6.2.2 SPI L_Q information unit 121

      11
    • 6.2.3 SPI data information unit 125

      11
    • 6.2.4 SPI data stream information unit 125

      11
    • 6.2.5 SPI status information unit 127

      11
• 7.0 SCSI commands 131

  11
  • 7.1 Command implementation requirements 131

    11
    • 7.1.1 Reserved 131

      11
  • 7.2 Command Descriptor Block (CDB) 131

    11
    • 7.2.1 Fixed and variable length Command Descriptor Block formats 133

      11
  • 7.3 Status 138

    11
    • 7.3.1 Status precedence 139

      12
  • 7.4 Command examples 140

    12
    • 7.4.1 Single command example 140

      12
    • 7.4.2 Disconnect example 141

      12
  • 7.5 Timing examples 142

    12
  • 7.6 Command processing considerations and exception conditions 142

    12
    • 7.6.1 Auto Contingent Allegiance or Contingent Allegiance 142

      12
      • 7.6.1.1 Logical Unit response to Auto Contingent Allegiance or Contingent Allegiance 142

        12
      • 7.6.1.2 Clearing an Auto Contingent Allegiance condition 143

        12
    • 7.6.2 Overlapped commands 143

      12
    • 7.6.3 Incorrect logical unit selection 144

      12
    • 7.6.4 Sense data 144

      12
      • 7.6.4.1 Asynchronous Event Reporting 144

        12
      • 7.6.4.2 Autosense 145

        12
    • 7.6.5 Unexpected RESELECTION phase 145

      12
    • 7.6.6 Unit Attention condition 146

      12
    • 7.6.7 Target hard reset 147

      12
    • 7.6.8 Logical unit reset 147

      12
  • 7.7 Queued tasks (formerly “queued I/O processes”) 147

    12
    • 7.7.1 Untagged task queuing 147

      12
    • 7.7.2 Tagged task queuing 148

      12
  • 7.8 Parameter rounding 149

    12
  • 7.9 Programmable operating definition 149

    12
  • 7.10 Incorrect initiator connection 150

    12
• 8.0 Drive features 151

  12
  • 8.1 S.M.A.R.T. system 151

    12
  • 8.2 Self-test operations 151

    12
    • 8.2.1 Default self-test 151

      12
    • 8.2.2 The short and extended self-tests 151

      12
    • 8.2.3 Self-test modes 152

      12
      • 8.2.3.1 Foreground mode 152

        12
      • 8.2.3.2 Background mode 152

        12
      • 8.2.3.3 Elements common to foreground and background self-test modes 153

        12
  • 8.3 Alternate error detection for the asynchronous information phases (AIP)-Command, Message, and Status 154

    12
    • 8.3.1 Error detection for asynchronous information phases 154

      12
    • 8.3.2 Protection code 154

      12
      • 8.3.2.1 Covered signals 155

        12
      • 8.3.2.2 Code description 157

        12
      • 8.3.2.3 Error detection properties 157

        12
    • 8.3.3 Protection code usage 157

      12
      • 8.3.3.1 Protection code transmission 158

        12
      • 8.3.3.2 Enabling protection code checking 158

        12
      • 8.3.3.3 Disabling protection code checking 158

        12
    • 8.3.4 Parity 158

      12
    • 8.3.5 Error handling 158

      12
  • 8.4 Removal and insertion of SCSI devices (popularly known as “hot plugging”) 158

    12
    • 8.4.1 Removal and insertion of SCSI devices overview 158

      12
    • 8.4.2 Case 1-Power off during removal or insertion 159

      12
    • 8.4.3 Case 2-RST signal asserted continuously during removal or insertion 159

      12
    • 8.4.4 Case 3-Current I/O processes not allowed during insertion or removal 159

      12
    • 8.4.5 Case 4-Current I/O process allowed during insertion or removal 159

      12
  • 8.5 SPI-3 to SCSI-2 terminology mapping 160

    12
• Figure 1. SCSI client-server model 4

  13
• Figure 2. Voltage and current definitions 18

  13
• Figure 3. LVD Signaling sense 18

  13
• Figure 4. ST latching data vs. DT latching data 35

  13
• Figure 5. ST synchronous transfer example 35

  13
• Figure 6. DT synchronous transfer example 36

  13
• Figure 7. Paced transfer example 36

  13
• Figure 8. Example of a SCSI bus with paced transfers 37

  13
• Figure 9. Use of P1 to establish data valid and data invalid states 72

  13
• Figure 10. Phase sequences for physical reconnection and selection using attention condition with information unit transfers disabled 79

  13
• Figure 11. Phase sequences for selection without using attention condition with information unit transfers disabled 79

  13
• Figure 12. Phase sequences for physical reconnection or selection without using attention condition/ with information unit transfers enabled 80

  13
• Figure 13. Phase sequences for selection with attention condition/physical reconnection and information unit transfers enabled 81

  13
• Figure 14. SPI information unit sequence during initial connection 115

  13
• Figure 15. SPI information unit sequence during data type transfers 116

  13
• Figure 16. SPI information unit sequence during data stream type transfers 117

  13
• Figure 17. SPI information unit sequence during status transfers 118

  13
• Figure 18. Single command example 140

  13
• Figure 19. Disconnect example 141

  13
• Figure 20. Protection code generator 157

  13
• 1.0 Interface requirements

  15
  • 1.1 How to use this interface manual

    15
    • 1.1.1 Scope of SCSI standards

      16
    • 1.1.2 Applicable standards

      17
  • 1.2 General interface description

    17
    • 1.2.1 Glossary

      18
    • 1.2.2 Keywords

      25
  • 1.3 Physical interface characteristics

    26
  • 1.4 Summary of SCSI messages

    26
• 2.0 SCSI bus

  27
  • 2.1 SCSI bus signals overview

    29
    • 2.1.1 Drive select

      31
    • 2.1.2 Signal values

      31
  • 2.2 Signal states

    31
    • 2.2.1 SE signals

      31
    • 2.2.2 LVD signals

      31
  • 2.3 OR-tied signals

    32
  • 2.4 Signal sources

    33
  • 2.5 SCSI bus timing

    34
    • 2.5.1 Arbitration delay

      40
    • 2.5.2 ATN transmit setup time

      40
    • 2.5.3 ATN receive setup time

      40
    • 2.5.4 Bus clear delay

      41
    • 2.5.5 Bus free delay

      41
    • 2.5.6 Bus set delay

      41
    • 2.5.7 Bus settle delay

      41
    • 2.5.8 Cable skew delay

      41
    • 2.5.9 Chip noise in receiver

      41
    • 2.5.10 Clock jitter

      41
    • 2.5.11 Crosstalk time shift

      41
    • 2.5.12 De-skewed data valid window

      42
    • 2.5.13 Flow control receive hold time

      42
    • 2.5.14 Flow control receive setup time

      42
    • 2.5.15 Flow control transmit hold time

      42
    • 2.5.16 Flow control transmit setup time

      42
    • 2.5.17 pCRC receive hold time

      42
    • 2.5.18 pCRC receive setup time

      42
    • 2.5.19 pCRC transmit hold time

      42
    • 2.5.20 pCRC transmit setup time

      42
    • 2.5.21 Data release delay

      43
    • 2.5.22 DIFFSENS voltage filter time

      43
    • 2.5.23 Offset induced time asymmetry

      43
    • 2.5.24 Physical disconnection delay

      43
    • 2.5.25 Power on to selection

      43
    • 2.5.26 QAS arbitration delay

      43
    • 2.5.27 QAS assertion delay

      43
    • 2.5.28 QAS release delay

      43
    • 2.5.29 QAS non-data phase REQ(ACK) period

      43
    • 2.5.30 Receive assertion period

      43
    • 2.5.31 Receive hold time

      43
    • 2.5.32 Receive internal hold time

      44
    • 2.5.33 Receive internal setup time

      44
    • 2.5.34 Receive negation period

      44
    • 2.5.35 Receive setup time

      44
    • 2.5.36 Receive REQ(ACK) period tolerance

      44
    • 2.5.37 Receive REQ assertion period with P_CRCA transitioning

      44
    • 2.5.38 Receive REQ negation period with P_CRCA transitioning

      44
    • 2.5.39 Receive skew compensation

      44
    • 2.5.40 Receiver amplitude time skew

      45
    • 2.5.41 REQ(ACK) period

      45
    • 2.5.42 Reset delay

      45
    • 2.5.43 Reset hold time

      45
    • 2.5.44 Reset to selection

      45
    • 2.5.45 Residual skew error

      45
    • 2.5.46 Selection abort time

      45
    • 2.5.47 Selection timeout delay

      45
    • 2.5.48 Signal timing skew

      45
    • 2.5.49 Skew correction range

      46
    • 2.5.50 Strobe offset tolerance

      46
    • 2.5.51 System deskew delay

      46
    • 2.5.52 System noise at launch

      46
    • 2.5.53 System noise at receiver

      46
    • 2.5.54 Time asymmetry

      46
    • 2.5.55 Transmit assertion period

      46
    • 2.5.56 Transmit hold time

      46
    • 2.5.57 Transmit ISI compensation

      46
    • 2.5.58 Transmit negation period

      46
    • 2.5.59 Transmit setup time

      47
    • 2.5.60 Transmit REQ(ACK) period tolerance

      47
    • 2.5.61 Transmit REQ assertion period with P_CRCA transitioning

      47
    • 2.5.62 Transmit REQ negation period with P_CRCA transitioning

      47
    • 2.5.63 Transmitter skew

      47
    • 2.5.64 Transmitter time asymmetry

      47
  • 2.6 Measurement points

    47
    • 2.6.1 SE Fast-5 and Fast-10 measurement points

      47
    • 2.6.2 SE Fast-20 measurement points

      47
    • 2.6.3 LVD measurement points

      48
  • 2.7 Clocking methods for data transfers

    48
  • 2.8 Paced transfer on a SCSI bus

    50
  • 2.9 Data transfer modes

    51
    • 2.9.1 Asynchronous transfers

      51
    • 2.9.2 Synchronous transfers

      51
    • 2.9.3 Paced transfers

      51
  • 2.10 ST DATA phase parallel transfers

    52
  • 2.11 DT DATA phase parallel transfers

    52
    • 2.11.1 Data group transfers

      52
    • 2.11.2 Information unit transfers

      52
  • 2.12 Negotiation

    53
    • 2.12.1 Negotiation algorithm

      53
    • 2.12.2 When to negotiate

      54
    • 2.12.3 Negotiable fields

      54
    • 2.12.4 Transfer agreements

      56
    • 2.12.5 Transfer period factor

      57
    • 2.12.6 REQ/ACK offset

      58
    • 2.12.7 Transfer width exponent

      58
    • 2.12.8 Protocol options

      59
      • 2.12.8.1 IU_REQ

        59
      • 2.12.8.2 DT_REQ

        60
      • 2.12.8.3 QAS_REQ

        60
      • 2.12.8.4 HOLD_MCS

        60
      • 2.12.8.5 WR_FLOW

        61
      • 2.12.8.6 RD_STRM

        61
      • 2.12.8.7 RTI (Retain Training Information)

        61
      • 2.12.8.8 PCOMP_EN

        61
    • 2.12.9 Negotiable field combinations

      62
    • 2.12.10 Message restrictions

      63
    • 2.12.11 Negotiation message sequences

      63
• 3.0 Logical characteristics

  65
  • 3.1 SCSI bus phases overview

    65
    • 3.1.1 BUS FREE phase

      65
      • 3.1.1.1 Unexpected and expected bus free phases

        65
      • 3.1.1.2 Expected bus free phases

        66
    • 3.1.2 Arbitration and QAS overview

      66
      • 3.1.2.1 Normal ARBITRATION phase

        67
      • 3.1.2.2 QAS protocol

        68
      • 3.1.2.3 QAS phase overview

        68
  • 3.2 SELECTION phase

    69
    • 3.2.1 Selection overview

      70
      • 3.2.1.1 Selection using attention condition

        70
        • 3.2.1.1.1 Starting the SELECTION phase when using attention condition

          70
        • 3.2.1.1.2 Information unit transfers disabled

          70
        • 3.2.1.1.3 Information unit transfers enabled

          70
        • 3.2.1.1.4 Selection using attention condition timeout procedure

          71
      • 3.2.1.2 Selection without using attention condition

        71
        • 3.2.1.2.1 Information unit transfers disabled or enabled

          71
        • 3.2.1.2.2 Selection without using attention condition time-out procedure

          71
  • 3.3 RESELECTION phase

    72
    • 3.3.1 RESELECTION phase overview

      72
    • 3.3.2 Physical reconnection

      72
    • 3.3.3 Physical reconnection timeout procedure

      73
  • 3.4 SCSI bus fairness

    73
  • 3.5 Information transfer phases

    74
    • 3.5.1 Asynchronous transfer

      75
    • 3.5.2 Synchronous transfer

      75
      • 3.5.2.1 ST synchronous data transfer

        75
      • 3.5.2.2 DT synchronous transfer

        76
        • 3.5.2.2.1 Information unit transfer

          76
          • 3.5.2.2.1.1 DT DATA IN phase information unit transfer exception condition handling

            77
          • 3.5.2.2.1.2 DT DATA OUT phase information unit transfer exception condition handling

            78
        • 3.5.2.2.2 Data group data field transfer

          78
          • 3.5.2.2.2.1 Data group pad field and pCRC field transfer to SCSI initiator port

            79
          • 3.5.2.2.2.2 Data group pad field and pCRC field transfer to SCSI target port

            80
    • 3.5.3 Paced transfer

      82
      • 3.5.3.1 Paced transfer training pattern

        82
        • 3.5.3.1.1 DT DATA IN phase training pattern

          83
        • 3.5.3.1.2 DT DATA OUT phase training pattern

          84
      • 3.5.3.2 P1 data valid/invalid state transitions

        85
        • 3.5.3.2.1 Starting pacing transfers at end of training pattern

          86
        • 3.5.3.2.2 Starting pacing transfers with no training pattern

          86
        • 3.5.3.2.3 Ending pacing transfers

          87
      • 3.5.3.3 Paced information unit transfer

        87
      • 3.5.3.4 Deskewing

        88
    • 3.5.4 Wide transfer

      88
  • 3.6 COMMAND phase

    89
    • 3.6.1 COMMAND phase description

      89
    • 3.6.2 COMMAND phase exception condition handling

      89
  • 3.7 DATA phase

    89
    • 3.7.1 DATA phase overview

      89
    • 3.7.2 DT DATA IN phase

      89
    • 3.7.3 DT DATA OUT phase

      90
    • 3.7.4 ST DATA IN phase

      90
    • 3.7.5 ST DATA OUT phase

      90
  • 3.8 STATUS phase

    90
    • 3.8.1 STATUS phase description

      90
    • 3.8.2 STATUS phase exception condition handling

      90
  • 3.9 MESSAGE phase

    90
    • 3.9.1 MESSAGE phase overview

      90
    • 3.9.2 MESSAGE IN phase

      90
      • 3.9.2.1 MESSAGE IN phase exception condition handling

        91
    • 3.9.3 MESSAGE OUT phase

      91
      • 3.9.3.1 MESSAGE OUT phase exception condition handling

        91
  • 3.10 Signal restrictions between phases

    91
  • 3.11 SCSI bus phase sequences

    92
    • 3.11.1 SCSI bus phase sequences overview

      92
    • 3.11.2 Phase sequences for physical reconnection and selection using attention condition with information unit transfers disabled

      92
    • 3.11.3 Phase sequences for selection without using attention condition with information unit transfers disabled

      93
    • 3.11.4 Phase sequences for physical reconnection or selection without using attention condition with information unit transfers enabled

      94
    • 3.11.5 Phase sequences for physical selection using attention condition with information unit transfers enabled

      95
  • 3.12 Data bus protection

    95
    • 3.12.1 Data bus protection overview

      95
    • 3.12.2 ST data bus protection using parity

      95
    • 3.12.3 DT data bus protection using CRC

      96
      • 3.12.3.1 DT data bus protection using CRC overview

        96
      • 3.12.3.2 Error detection capabilities

        96
      • 3.12.3.3 Order of bytes in the CRC field

        96
• 4.0 Message system specification

  97
  • 4.1 General message protocols and formats

    97
  • 4.2 Message formats

    97
    • 4.2.1 One-byte messages

      98
    • 4.2.2 Two-byte messages

      98
    • 4.2.3 Extended messages

      98
  • 4.3 Message categories

    99
    • 4.3.1 LINK CONTROL MESSAGES

      99
    • 4.3.2 DISCONNECT

      101
    • 4.3.3 IDENTIFY

      101
    • 4.3.4 IGNORE WIDE RESIDUE

      102
    • 4.3.5 INITIATOR DETECTED ERROR

      103
    • 4.3.6 LINKED COMMAND COMPLETE

      103
    • 4.3.7 MESSAGE PARITY ERROR

      103
    • 4.3.8 MESSAGE REJECT

      103
    • 4.3.9 MODIFY DATA POINTER

      103
    • 4.3.10 MODIFY BIDIRECTIONAL DATA POINTER

      104
    • 4.3.11 NO OPERATION

      105
    • 4.3.12 PARALLEL PROTOCOL REQUEST

      106
      • 4.3.12.1 PARALLEL PROTOCOL REQUEST

        109
    • 4.3.13 QAS REQUEST

      110
    • 4.3.14 RESTORE POINTERS

      110
    • 4.3.15 SAVE DATA POINTERS

      110
    • 4.3.16 SYNCHRONOUS DATA TRANSFER REQUEST

      111
      • 4.3.16.1 Target initiated SDTR negotiation

        113
      • 4.3.16.2 Initiator initiated SDTR negotiation

        113
    • 4.3.17 TASK COMPLETE

      113
    • 4.3.18 WIDE DATA TRANSFER REQUEST

      114
      • 4.3.18.1 Target initiated WDTR negotiation

        115
      • 4.3.18.2 Initiator initiated Wide Data Transfer Request (WDTR) negotiation

        116
  • 4.4 Task attribute messages

    116
    • 4.4.1 Task attribute message overview and codes

      116
    • 4.4.2 ACA (AUTO CONTINGENT ALLEGIANCE)

      117
    • 4.4.3 HEAD OF QUEUE

      118
    • 4.4.4 ORDERED

      118
    • 4.4.5 SIMPLE

      118
  • 4.5 Task management messages

    119
    • 4.5.1 Task management message codes

      119
    • 4.5.2 ABORT TASK

      119
    • 4.5.3 ABORT TASK SET

      120
    • 4.5.4 CLEAR ACA

      120
    • 4.5.5 CLEAR TASK SET

      120
    • 4.5.6 LOGICAL UNIT RESET

      120
    • 4.5.7 TARGET RESET

      120
• 5.0 Miscellaneous SCSI bus characteristics

  121
  • 5.1 Attention condition

    121
  • 5.2 Bus reset condition

    122
  • 5.3 Hard reset

    122
  • 5.4 Reset events

    123
    • 5.4.1 Bus reset event

      123
    • 5.4.2 Power on reset event

      123
    • 5.4.3 Target reset event

      123
    • 5.4.4 Transceiver mode change reset event

      123
  • 5.5 Asynchronous condition recovery

    123
    • 5.5.1 SCSI pointers

      123
    • 5.5.2 Active pointers

      124
    • 5.5.3 Saved pointers

      124
  • 5.6 Command processing considerations and exception conditions

    125
    • 5.6.1 Command processing considerations and exception conditions overview

      125
    • 5.6.2 Asynchronous event notification

      125
    • 5.6.3 Incorrect initiator connection

      125
    • 5.6.4 Unexpected RESELECTION phase

      126
• 6.0 SPI information units

  127
  • 6.1 Information unit transfer logical operations

    127
  • 6.2 SPI information units

    132
    • 6.2.1 SPI command information unit

      132
    • 6.2.2 SPI L_Q information unit

      135
    • 6.2.3 SPI data information unit

      139
    • 6.2.4 SPI data stream information unit

      139
    • 6.2.5 SPI status information unit

      141
• 7.0 SCSI commands

  145
  • 7.1 Command implementation requirements

    145
    • 7.1.1 Reserved

      145
  • 7.2 Command Descriptor Block (CDB)

    145
    • 7.2.1 Fixed and variable length Command Descriptor Block formats

      147
  • 7.3 Status

    152
    • 7.3.1 Status precedence

      153
  • 7.4 Command examples

    154
    • 7.4.1 Single command example

      154
    • 7.4.2 Disconnect example

      155
  • 7.5 Timing examples

    156
  • 7.6 Command processing considerations and exception conditions

    156
    • 7.6.1 Auto Contingent Allegiance or Contingent Allegiance

      156
      • 7.6.1.1 Logical Unit response to Auto Contingent Allegiance or Contingent Allegiance

        156
      • 7.6.1.2 Clearing an Auto Contingent Allegiance condition

        157
    • 7.6.2 Overlapped commands

      157
    • 7.6.3 Incorrect logical unit selection

      158
    • 7.6.4 Sense data

      158
      • 7.6.4.1 Asynchronous Event Reporting

        158
      • 7.6.4.2 Autosense

        159
    • 7.6.5 Unexpected RESELECTION phase

      159
    • 7.6.6 Unit Attention condition

      160
    • 7.6.7 Target hard reset

      161
    • 7.6.8 Logical unit reset

      161
  • 7.7 Queued tasks (formerly “queued I/O processes”)

    161
    • 7.7.1 Untagged task queuing

      161
    • 7.7.2 Tagged task queuing

      162
  • 7.8 Parameter rounding

    163
  • 7.9 Programmable operating definition

    163
  • 7.10 Incorrect initiator connection

    164
• 8.0 Drive features

  165
  • 8.1 S.M.A.R.T. system

    165
  • 8.2 Self-test operations

    165
    • 8.2.1 Default self-test

      165
    • 8.2.2 The short and extended self-tests

      165
    • 8.2.3 Self-test modes

      166
      • 8.2.3.1 Foreground mode

        166
      • 8.2.3.2 Background mode

        166
      • 8.2.3.3 Elements common to foreground and background self-test modes

        167
  • 8.3 Alternate error detection for the asynchronous information phases (AIP)- Command, Message, and Status

    168
    • 8.3.1 Error detection for asynchronous information phases

      168
    • 8.3.2 Protection code

      168
      • 8.3.2.1 Covered signals

        169
      • 8.3.2.2 Code description

        171
      • 8.3.2.3 Error detection properties

        171
    • 8.3.3 Protection code usage

      171
      • 8.3.3.1 Protection code transmission

        172
      • 8.3.3.2 Enabling protection code checking

        172
      • 8.3.3.3 Disabling protection code checking

        172
    • 8.3.4 Parity

      172
    • 8.3.5 Error handling

      172
  • 8.4 Removal and insertion of SCSI devices (popularly known as “hot plugging”)

    172
    • 8.4.1 Removal and insertion of SCSI devices overview

      172
    • 8.4.2 Case 1-Power off during removal or insertion

      173
    • 8.4.3 Case 2-RST signal asserted continuously during removal or insertion

      173
    • 8.4.4 Case 3-Current I/O processes not allowed during insertion or removal

      173
    • 8.4.5 Case 4-Current I/O process allowed during insertion or removal

      173
  • 8.5 SPI-3 to SCSI-2 terminology mapping

    174
    • A

      175
    • B

      175
    • C

      175
    • D

      176
    • E

      177
    • F

      177
    • G

      177
    • H

      177
    • I

      177
    • K

      178
    • L

      178
    • M

      178
    • N

      179
    • O

      179
    • P

      179
    • Q

      180
    • R

      180
    • S

      181
    • T

      182
    • U

      183
    • V

      183
    • W

      183