User ManualTable of ContentsTable of Contents3Preface141 Overview161.1 General RapidIO System161.1.1 RapidIO Architectural Hierarchy161.1.2 RapidIO Interconnect Architecture181.1.3 Physical Layer 1x/4x LP-Serial Specification181.2 RapidIO Feature Support in SRIO191.3 Standards201.4 External Devices Requirements201.5 TI Devices Supported By This Document202 SRIO Functional Description212.1 Overview212.1.1 Peripheral Data Flow212.1.2 SRIO Packets222.1.2.1 Operation Sequence222.1.2.2 Example Packet – Streaming Write232.1.2.3 Control Symbols242.1.2.4 SRIO Packet Type252.2 SRIO Pins252.3 Functional Operation262.3.1 Component Block Diagram262.3.2 SERDES Macro and its Configurations282.3.2.1 Enabling the PLL282.3.2.2 Enabling the Receiver302.3.2.3 Enabling the Transmitter332.3.2.4 SERDES Configuration Example352.3.3 Direct I/O Operation352.3.3.1 Detailed Data Path Description392.3.3.2 Direct I/O TX Operation402.3.3.3 Direct I/O RX Operation422.3.3.4 Reset and Power Down State432.3.4 Message Passing432.3.4.1 RX Operation442.3.4.2 TX Operation512.3.4.3 Reset and Power Down State592.3.4.4 Message Passing Software Requirements602.3.5 Maintenance632.3.6 Doorbell Operation632.3.7 Atomic Operations652.3.8 Congestion Control652.3.8.1 Detailed Description662.3.9 Endianness682.3.9.1 Translation for MMR space692.3.9.2 Endian Conversion (TMS320TCI6482)692.3.10 Reset and Power Down702.3.10.1 Reset and Power Down Summary712.3.10.2 Enable and Enable Status Registers712.3.10.3 Software Shutdown Details742.3.11 Emulation742.3.12 TX Buffers, Credit, and Packet Reordering752.3.12.1 Multiple Ports With 1x Operation752.3.12.2 Single Port With 1x or 4x Operation762.3.12.3 Unavailable Outbound Credit762.3.13 Initialization Example772.3.13.1 Enabling the SRIO Peripheral772.3.13.2 PLL, Ports, Device ID and Data Rate Initializations772.3.13.3 Peripheral Initializations782.3.14 Bootload Capability792.3.14.1 Configuration and Operation792.3.14.2 Bootload Data Movement802.3.14.3 Device Wakeup802.3.15 RX Multicast Support, Daisy Chain Operation and Packet Forwarding802.3.15.1 RX Multicast Support802.3.15.2 Daisy Chain Operation and Packet Forwarding812.3.15.3 Enabling Multicast and Packet Forwarding813 Logical/Transport Error Handling and Logging834 Interrupt Conditions854.1 CPU Interrupts854.2 General Description854.3 Interrupt Condition Status and Clear Registers864.3.1 Doorbell Interrupt Condition Status and Clear Registers874.3.2 CPPI Interrupt Condition Status and Clear Registers884.3.3 LSU Interrupt Condition Status and Clear Registers894.3.4 Error, Reset, and Special Event Interrupt Condition Status and Clear Registers914.4 Interrupt Condition Routing Registers934.4.1 Doorbell Interrupt Condition Routing Registers934.4.1.1 CPPI Interrupt Condition Routing Registers944.4.1.2 LSU Interrupt Condition Routing Registers954.4.1.3 Error, Reset, and Special Event Interrupt Condition Routing Registers964.5 Interrupt Status Decode Registers974.6 Interrupt Generation994.7 Interrupt Pacing994.8 Interrupt Handling1005 SRIO Registers1025.1 Introduction1025.2 Peripheral Identification Register (PID)1115.3 Peripheral Control Register (PCR)1125.4 Peripheral Settings Control Register (PER_SET_CNTL)1135.5 Peripheral Global Enable Register (GBL_EN)1165.6 Peripheral Global Enable Status Register (GBL_EN_STAT)1175.7 Block n Enable Register (BLKn_EN)1195.8 Block n Enable Status Register (BLKn_EN_STAT)1205.9 RapidIO DEVICEID1 Register (DEVICEID_REG1)1215.10 RapidIO DEVICEID2 Register (DEVICEID_REG2)1225.11 Packet Forwarding Register n for 16-Bit Device IDs (PF_16B_CNTLn)1235.12 Packet Forwarding Register n for 8-Bit Device IDs (PF_8B_CNTLn)1245.13 SERDES Receive Channel Configuration Register n (SERDES_CFGRXn_CNTL)1255.14 SERDES Transmit Channel Configuration Register n (SERDES_CFGTXn_CNTL)1285.15 SERDES Macro Configuration Register n (SERDES_CFGn_CNTL)1305.16 DOORBELLn Interrupt Condition Status Register (DOORBELLn_ICSR)1325.17 DOORBELLn Interrupt Condition Clear Register (DOORBELLn_ICCR)1335.18 RX CPPI Interrupt Status Register (RX_CPPI_ICSR)1345.19 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR)1355.20 TX CPPI Interrupt Status Register (TX_CPPI_ICSR)1365.21 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR)1375.22 LSU Interrupt Condition Status Register (LSU_ICSR)1385.23 LSU Interrupt Condition Clear Register (LSU_ICCR)1415.24 Error, Reset, and Special Event Interrupt Condition Status Register (ERR_RST_EVNT_ICSR)1425.25 Error, Reset, and Special Event Interrupt Condition Clear Register (ERR_RST_EVNT_ICCR)1435.26 DOORBELLn Interrupt Condition Routing Registers (DOORBELLn_ICRR and DOORBELLn_ICRR2)1445.27 RX CPPI Interrupt Condition Routing Registers (RX_CPPI_ICRR and RX_CPPI_ICRR2)1455.28 TX CPPI Interrupt Condition Routing Registers (TX_CPPI_ICRR and TX_CPPI_ICRR2)1465.29 LSU Interrupt Condition Routing Registers (LSU_ICRR0–LSU_ICRR3)1475.30 Error, Reset, and Special Event Interrupt Condition Routing Registers (ERR_RST_EVNT_ICRR, ERR_RST_EVNT_ICRR2, and ERR_RST_EVNT_ICRR3)1495.31 Interrupt Status Decode Register (INTDSTn_DECODE)1505.32 INTDSTn Interrupt Rate Control Register (INTDSTn_RATE_CNTL)1545.33 LSUn Control Register 0 (LSUn_REG0)1555.34 LSUn Control Register 1 (LSUn_REG1)1565.35 LSUn Control Register 2 (LSUn_REG2)1575.36 LSUn Control Register 3 (LSUn_REG3)1585.37 LSUn Control Register 4 (LSUn_REG4)1595.38 LSUn Control Register 5 (LSUn_REG5)1605.39 LSUn Control Register 6 (LSUn_REG6)1615.40 LSUn Congestion Control Flow Mask Register (LSUn_FLOW_MASKS)1625.41 Queue n Transmit DMA Head Descriptor Pointer Register (QUEUEn_TXDMA_HDP)1645.42 Queue n Transmit DMA Completion Pointer Register (QUEUEn_TXDMA_CP)1655.43 Queue n Receive DMA Head Descriptor Pointer Register (QUEUEn_RXDMA_HDP)1665.44 Queue n Receive DMA Completion Pointer Register (QUEUEn_RXDMA_CP)1675.45 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN)1685.46 Transmit CPPI Supported Flow Mask Registers (TX_CPPI_FLOW_MASKS[0–7])1695.47 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN)1725.48 Receive CPPI Control Register (RX_CPPI_CNTL)1735.49 Transmit CPPI Weighted Round Robin Control Registers (TX_QUEUE_CNTL[0–3])1745.50 Mailbox to Queue Mapping Registers (RXU_MAP_Ln and RXU_MAP_Hn)1775.51 Flow Control Table Entry Register n (FLOW_CNTLn)1815.52 Device Identity CAR (DEV_ID)1825.53 Device Information CAR (DEV_INFO)1835.54 Assembly Identity CAR (ASBLY_ID)1845.55 Assembly Information CAR (ASBLY_INFO)1855.56 Processing Element Features CAR (PE_FEAT)1865.57 Source Operations CAR (SRC_OP)1885.58 Destination Operations CAR (DEST_OP)1895.59 Processing Element Logical Layer Control CSR (PE_LL_CTL)1905.60 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR)1915.61 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR)1925.62 Base Device ID CSR (BASE_ID)1935.63 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK)1945.64 Component Tag CSR (COMP_TAG)1955.65 1x/4x LP Serial Port Maintenance Block Header Register (SP_MB_HEAD)1965.66 Port Link Time-Out Control CSR (SP_LT_CTL)1975.67 Port Response Time-Out Control CSR (SP_RT_CTL)1985.68 Port General Control CSR (SP_GEN_CTL)1995.69 Port Link Maintenance Request CSR n (SPn_LM_REQ)2005.70 Port Link Maintenance Response CSR n (SPn_LM_RESP)2015.71 Port Local AckID Status CSR n (SPn_ACKID_STAT)2025.72 Port Error and Status CSR n (SPn_ERR_STAT)2035.73 Port Control CSR n (SPn_CTL)2065.74 Error Reporting Block Header Register (ERR_RPT_BH)2095.75 Logical/Transport Layer Error Detect CSR (ERR_DET)2105.76 Logical/Transport Layer Error Enable CSR (ERR_EN)2125.77 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT)2145.78 Logical/Transport Layer Address Capture CSR (ADDR_CAPT)2155.79 Logical/Transport Layer Device ID Capture CSR (ID_CAPT)2165.80 Logical/Transport Layer Control Capture CSR (CTRL_CAPT)2175.81 Port-Write Target Device ID CSR (PW_TGT_ID)2185.82 Port Error Detect CSR n (SPn_ERR_DET)2195.83 Port Error Rate Enable CSR n (SPn_RATE_EN)2215.84 Port n Attributes Error Capture CSR 0 (SPn_ERR_ATTR_CAPT_DBG0)2235.85 Port n Error Capture CSR 1 (SPn_ERR_CAPT_DBG1)2245.86 Port n Error Capture CSR 2 (SPn_ERR_CAPT_DBG2)2255.87 Port n Error Capture CSR 3 (SPn_ERR_CAPT_DBG3)2265.88 Port n Error Capture CSR 4 (SPn_ERR_CAPT_DBG4)2275.89 Port Error Rate CSR n (SPn_ERR_RATE)2285.90 Port Error Rate Threshold CSR n (SPn_ERR_THRESH)2295.91 Port IP Discovery Timer for 4x Mode Register (SP_IP_DISCOVERY_TIMER)2305.92 Port IP Mode CSR (SP_IP_MODE)2315.93 Port IP Prescaler Register (IP_PRESCAL)2335.94 Port-Write-In Capture CSRs (SP_IP_PW_IN_CAPT[0–3])2345.95 Port Reset Option CSR n (SPn_RST_OPT)2355.96 Port Control Independent Register n (SPn_CTL_INDEP)2365.97 Port Silence Timer n Register (SPn_SILENCE_TIMER)2385.98 Port Multicast-Event Control Symbol Request Register n (SPn_MULT_EVNT_CS)2395.99 Port Control Symbol Transmit n Register (SPn_CS_TX)240Index241Size: 2.5 MBPages: 256Language: EnglishOpen manual