Texas TMS3320C5515 User Manuals

Table of Contents

• Table of Contents

  3
• Preface

  9
• 1 System Control

  13
  • 1.1 Introduction

    13
    • 1.1.1 Block Diagram

      13
    • 1.1.2 CPU Core

      14
    • 1.1.3 FFT Hardware Accelerator

      14
      • 1.1.3.1 Using FFT Accelerator ROM routines

        14
    • 1.1.4 Power Management

      15
    • 1.1.5 Peripherals

      15
  • 1.2 System Memory

    16
    • 1.2.1 Program/Data Memory Map

      16
      • 1.2.1.1 On-Chip Dual-Access RAM (DARAM)

        17
      • 1.2.1.2 On-Chip Single-Access RAM (SARAM)

        18
      • 1.2.1.3 On-Chip Single-Access Read-Only Memory (SAROM)

        19
      • 1.2.1.4 External Memory

        19
        • 1.2.1.4.1 Asynchronous EMIF Interface

          19
      • 1.2.1.5 Synchronous EMIF Interface

        19
    • 1.2.2 I/O Memory Map

      20
  • 1.3 Device Clocking

    20
    • 1.3.1 Overview

      20
    • 1.3.2 Clock Domains

      23
  • 1.4 System Clock Generator

    23
    • 1.4.1 Overview

      23
    • 1.4.2 Functional Description

      24
      • 1.4.2.1 Multiplier and Dividers

        24
      • 1.4.2.2 Powering Down and Powering Up the System PLL

        24
      • 1.4.2.3 CLKOUT Pin

        25
      • 1.4.2.4 DSP Reset Conditions of the System Clock Generator

        26
        • 1.4.2.4.1 Clock Generator During Reset

          26
        • 1.4.2.4.2 Clock Generator After Reset

          26
    • 1.4.3 Configuration

      26
      • 1.4.3.1 BYPASS MODE

        26
        • 1.4.3.1.1 Entering and Exiting the BYPASS MODE

          26
        • 1.4.3.1.2 Register Bits Used in the BYPASS MODE

          27
        • 1.4.3.1.3 Setting the System Clock Frequency In the BYPASS MODE

          27
      • 1.4.3.2 PLL MODE

        27
        • 1.4.3.2.1 Entering and Exiting the PLL MODE

          27
        • 1.4.3.2.2 Register Bits Used in the PLL Mode

          27
        • 1.4.3.2.3 Frequency Ranges for Internal Clocks

          28
        • 1.4.3.2.4 Setting the Output Frequency for the PLL MODE

          28
        • 1.4.3.2.5 Lock Time

          29
        • 1.4.3.2.6 Software Steps To Modify Multiplier and Divider Ratios

          29
    • 1.4.4 Clock Generator Registers

      29
      • 1.4.4.1 Clock Generator Control Register 1 (CGCR1) [1C20h]

        30
      • 1.4.4.2 Clock Generator Control Register 2 (CGCR2) [1C21h]

        30
      • 1.4.4.3 Clock Generator Control Register 3 (CGCR3) [1C22h]

        31
      • 1.4.4.4 Clock Generator Control Register 4 (CGCR4) [1C23h]

        31
      • 1.4.4.5 Clock Configuration Register 1 (CCR1) [1C1Eh]

        32
      • 1.4.4.6 Clock Configuration Register 2 (CCR2) [1C1Fh]

        32
  • 1.5 Power Management

    33
    • 1.5.1 Overview

      33
    • 1.5.2 Power Domains

      33
    • 1.5.3 Clock Management

      34
      • 1.5.3.1 CPU Domain Clock Gating

        35
        • 1.5.3.1.1 Idle Configuration Register (ICR) [0001h] and IDLE Status Register (ISTR) [0002h]

          36
        • 1.5.3.1.2 Valid Idle Configurations

          37
        • 1.5.3.1.3 Clock Configuration Process

          38
      • 1.5.3.2 Peripheral Domain Clock Gating

        38
        • 1.5.3.2.1 Peripheral Clock Gating Configuration Registers (PCGCR1 and PCGCR2) [1C02 - 1C03h]

          39
        • 1.5.3.2.2 Peripheral Clock Stop Request/Acknowledge Register (CLKSTOP) [1C3Ah]

          42
        • 1.5.3.2.3 Clock Configuration Process

          43
      • 1.5.3.3 Clock Generator Domain Clock Gating

        43
      • 1.5.3.4 USB Domain Clock Gating

        43
        • 1.5.3.4.1 Clock Configuration Process

          44
        • 1.5.3.4.2 USB System Control Register (USBSCR) [1C32h]

          44
      • 1.5.3.5 RTC Domain Clock Gating

        45
    • 1.5.4 Static Power Management

      46
      • 1.5.4.1 RTC Power Management Register (RTCPMGT) [1930h]

        46
      • 1.5.4.2 RTC Interrupt Flag Register (RTCINTFL) [1920h]

        47
      • 1.5.4.3 Internal Memory Low Power Modes

        48
        • 1.5.4.3.1 RAM Sleep Mode Control Register 1 (RAMSLPMDCNTLR1) [1C28h]

          48
    • 1.5.5 Power Configurations

      50
      • 1.5.5.1 IDLE2 Procedure

        51
      • 1.5.5.2 IDLE3 Procedure

        52
      • 1.5.5.3 Core Voltage Scaling

        52
  • 1.6 Interrupts

    53
    • 1.6.1 IFR and IER Registers

      54
    • 1.6.2 Interrupt Timing

      55
    • 1.6.3 Timer Interrupt Aggregation Flag Register (TIAFR) [1C14h]

      56
    • 1.6.4 GPIO Interrupt Enable and Aggregation Flag Registers

      56
    • 1.6.5 DMA Interrupt Enable and Aggregation Flag Registers

      56
  • 1.7 System Configuration and Control

    57
    • 1.7.1 Overview

      57
    • 1.7.2 Device Identification

      57
      • 1.7.2.1 Die ID Register 0 (DIEIDR0) [1C40h]

        58
      • 1.7.2.2 Die ID Register 1 (DIEIDR1) [1C41h]

        58
      • 1.7.2.3 Die ID Register 2 (DIEIDR2) [1C42h]

        58
      • 1.7.2.4 Die ID Register 3 (DIEIDR3[15:0]) [1C43h]

        59
      • 1.7.2.5 Die ID Register 4 (DIEIDR4) [1C44h]

        59
      • 1.7.2.6 Die ID Register 5 (DIEIDR5) [1C45h]

        59
      • 1.7.2.7 Die ID Register 6 (DIEIDR6) [1C46h]

        60
      • 1.7.2.8 Die ID Register 7 (DIEIDR7) [1C47h]

        60
    • 1.7.3 Device Configuration

      61
      • 1.7.3.1 External Bus Selection Register (EBSR)

        61
      • 1.7.3.2 LDO Control Register [7004h]

        63
      • 1.7.3.3 LDO Control

        63
      • 1.7.3.4 Output Slew Rate Control Register (OSRCR) [1C16h]

        66
      • 1.7.3.5 Pull-Up/Pull-Down Inhibit Register (PDINHIBR1, PDINHIBR2, and PDINHIBR3 [1C17h, 1C18h, and 1C19h]

        67
    • 1.7.4 DMA Controller Configuration

      70
      • 1.7.4.1 DMA Synchronization Events

        71
      • 1.7.4.2 DMA Configuration Registers

        71
        • 1.7.4.2.1 DMA Interrupt Flag Register (DMAIFR) [1C30h] and DMA Interrupt Enable Register (DMAIER) [1C31h]

          72
        • 1.7.4.2.2 DMAn Channel Event Source Registers (DMAnCESR1 and DMAnCESR2) [1C1Ah, 1C1Bh, 1C1Ch, 1C1Dh, 1C36h, 1C37h, 1C38h, and 1C39h]

          73
    • 1.7.5 Peripheral Reset

      73
      • 1.7.5.1 Peripheral Software Reset Counter Register (PSRCR) [1C04h]

        74
      • 1.7.5.2 Peripheral Reset Control Register (PRCR) [1C05h]

        74
    • 1.7.6 EMIF and USB Byte Access

      75
      • 1.7.6.1 EMIF System Control Register (ESCR) [1C33h]

        76
    • 1.7.7 EMIF Clock Divider Register (ECDR) [1C26h]

      77