Intel L5530 AT80602002937AB Manual De Usuario
Los códigos de productos
AT80602002937AB
Intel
®
Xeon
®
Processor 5500 Series Datasheet, Volume 1
87
Signal Definitions
PSI#
O
Processor Power Status Indicator signal. This signal is asserted when maximum
possible processor core current consumption is less than 20A, Assertion of this
signal is an indication that the VR controller does not currently need to be able to
provide ICC above 20A, and the VR controller can use this information to move to
more efficient operation point. This signal will de-assert at least 3.3 µs before the
current consumption will exceed 20A. The minimum PSI# assertion time is 1 BCLK.
The minimum PSI# de-assertion time is 3.3 us.
This pin does not require a pull-down. For platforms which could experience false
This pin does not require a pull-down. For platforms which could experience false
PSI# assertions during power-up if this pin is left floating, a pull-up may be used
(1K-5K). Otherwise, it can be left floating. For boards currently pulling this signal to
Vss, this is not a critical change to make immediately, but it is recommended for
production builds.
RESET#
I
Asserting the RESET# signal resets the processor to a known state and invalidates
its internal caches without writing back any of their contents. Note some PLL, Intel
QuickPath Interconnect and error states are not effected by reset and only
VCCPWRGOOD forces them to a known state. For a power-on Reset, RESET# must
stay active for at least one millisecond after VCC and BCLK have reached their
proper specifications. RESET# must not be kept asserted for more than 10 ms
while VCCPWRGOOD is asserted. RESET# must be held deasserted for at least one
millisecond before it is asserted again. RESET# must be held asserted before
VCCPWRGOOD is asserted. This signal does not have on-die termination and must
be terminated on the system board. RESET# is a common clock signal.
SKTOCC#
O
Socket occupied, platform must sense a VSS at this pin to enable POWER_ON.
TCK
I
TCK (Test Clock) provides the clock input for the processor Test Bus (also known as
the Test Access Port).
TDI
I
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
TDO
O
TDO (Test Data Out) transfers serial test data out of the processor. TDO provides
the serial output needed for JTAG specification support.
THERMTRIP#
O
Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a level beyond which permanent silicon damage may
occur. Measurement of the temperature is accomplished through an internal
thermal sensor. Once activated, the processor will stop all execution and shut down
all PLLs. To further protect the processor, its core voltage (V
CC
), V
TTA
V
TTD
and V
DDQ
must be removed following the assertion of THERMTRIP#. Once activated,
THERMTRIP# remains latched until RESET# is asserted. While the assertion of the
RESET# signal may de-assert THERMTRIP#, if the processor's junction temperature
remains at or above the trip level, THERMTRIP# will again be asserted after
RESET# is de-asserted.
TMS
I
TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.
TRST#
I
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven
low during power on Reset.
V
CC_SENSE
V
SS_SENSE
O
O
O
V
CC_SENSE
and V
SS_SENSE
provide an isolated, low impedance connection to the
processor core voltage and ground. They can used to sense or measure power near
the silicon with little noise.
V
CC
I
Power for processor core.
VCCPWRGOOD
I
VCCPWRGOOD (Power Good) is a processor input. The processor requires this
signal to be a clean indication that BCLK, V
CC
, V
CCPLL
, V
TTA
and V
TTD
supplies are
stable and within their specifications. 'Clean' implies that the signal will remain low
(capable of sinking leakage current), without glitches, from the time that the power
supplies are turned on until they come within specification. The signal must then
transition monotonically to a high state. VCCPWRGOOD can be driven inactive at
any time, but BCLK and power must again be stable before a subsequent rising
edge of VCCPWRGOOD. In addition at the time VCCPWRGOOD is asserted RESET#
must be active. The PWRGOOD signal must be supplied to the processor; it is used
to protect internal circuits against voltage sequencing issues. It should be driven
high throughout boundary scan operation.
V
CCPLL
I
Analog Power for Clocks.
V
DDQ
I
Power supply for the DDR3 interface.
Table 5-1.
Signal Definitions (Sheet 3 of 4)
Name
Type
Description
Notes