Renesas rl78 Manual De Usuario
RL78/G1A
CHAPTER 13 SERIAL INTERFACE IICA
(1) Master device operation
(a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception)
(i) When WTIM0 = 0
ST
AD6 to AD0
R/W ACK
D7 to D0
D7 to D0
ACK
ACK
SP
SPT0 = 1
↓
3
4
5
2
1
1: IICS0 = 1000×110B
2: IICS0 = 1000×000B
3: IICS0 = 1000×000B (Sets the WTIM0 bit to 1)
Note
4: IICS0 = 1000××00B (Sets the SPT0 bit to 1)
Note
5: IICS0 = 00000001B
Note To generate a stop condition, set the WTIM0 bit to 1 and change the timing for generating the INTIICA0
interrupt request signal.
Remark
: Always
generated
: Generated only when SPIE0 = 1
×:
Don’t
care
(ii) When WTIM0 = 1
ST
AD6 to AD0
R/W ACK
D7 to D0
D7 to D0
ACK
ACK
SP
SPT0 = 1
↓
3
4
2
1
1: IICS0 = 1000×110B
2: IICS0 = 1000×100B
3: IICS0 = 1000××00B (Sets the SPT0 bit to 1)
4: IICS0 = 00000001B
Remark
: Always
generated
: Generated only when SPIE0 = 1
×:
Don’t
care
R01UH0305EJ0200 Rev.2.00
617
Jul 04, 2013