Renesas SH7709S Manual De Usuario
Rev. 5.00, 09/03, page 103 of 760
Section 5 Cache
5.1
Overview
5.1.1
Features
The cache specifications are listed in table 5.1.
Table 5.1
Cache Specifications
Parameter
Specification
Capacity
16 kbytes
Structure
Instruction/data mixed, 4-way set associative
Locking
Way 2 and way 3 are lockable
Line size
16 bytes
Number of entries
256 entries/way
Write system
P0, P1, P3, U0: Write-back/write-through selectable
Replacement method
Least-recently-used (LRU) algorithm
5.1.2
Cache Structure
The cache mixes data and instructions and uses a 4-way set associative system. It is composed of
four ways (banks), each of which is divided into an address section and a data section. Each of the
address and data sections is divided into 256 entries. The data section of the entry is called a line.
Each line consists of 16 bytes (4 bytes
four ways (banks), each of which is divided into an address section and a data section. Each of the
address and data sections is divided into 256 entries. The data section of the entry is called a line.
Each line consists of 16 bytes (4 bytes
×
4). The data capacity per way is 4 kbytes (16 bytes
×
256
entries), with a total of 16 kbytes in the cache as a whole (4 ways). Figure 5.1 shows the cache
structure.
structure.