Renesas SH7709S Manual De Usuario
Rev. 5.00, 09/03, page 321 of 760
IIIIR
R
R
RQ
Q
Q
QO
O
O
OU
U
U
UT
TT
T Pin Assertion Conditions:
•
When a memory refresh request has been generated but the refresh cycle has not yet begun
•
When an interrupt is generated with an interrupt request level higher than the setting of the
interrupt mask bits (I3–I0) in the status register (SR). (This does not depend on the SR.BL bit.)
interrupt mask bits (I3–I0) in the status register (SR). (This does not depend on the SR.BL bit.)
10.3.9
Bus Pull-Up
With the SH7709S, address pin pull-up can be performed when the bus is released by setting the
PULA bit in BCR1 to 1. The address pins are pulled up for a 4-clock period after
PULA bit in BCR1 to 1. The address pins are pulled up for a 4-clock period after
BACK is
asserted. Figure 10.41 shows the address pin pull-up timing. Similarly, data pin pull-up can be
performed by setting the PULD bit in BCR1 to 1. The data pins should be pulled up when the data
bus is not in use. The data pin pull-up timing for a read cycle is shown in figure 10.42, and the
timing for a write cycle in figure 10.43.
performed by setting the PULD bit in BCR1 to 1. The data pins should be pulled up when the data
bus is not in use. The data pin pull-up timing for a read cycle is shown in figure 10.42, and the
timing for a write cycle in figure 10.43.
Hi-Z
Pull-up
CKIO
A25 to A0
BACK
Figure 10.41 Pull-Up Timing for Pins A25 to A0