Renesas SH7709S Manual De Usuario

Rev. 5.00, 09/03, page 384 of 760

In this example, DMA transfer is performed between the on-chip A/D converter (transfer source)
and the external memory (transfer destination) with the address reload function on. Table 11.9
shows the transfer conditions and register settings.

Transfer source: On-chip A/D converter

SAR2

H'04000080

Transfer destination: Internal memory

DAR2

H'00400000

Number of transfers: 128 (reloading 32 times)

DMATCR2

H'00000080

Transfer source address: Incremented

CHCR2

H'00089E35

Transfer destination address: Decremented

Transfer request source: A/D converter

Bus mode: Burst

Transfer unit: Longword

Interrupt request generated at end of transfer

Channel priority order: 0 > 2 > 3 > 1

DMAOR

H'0101

When the address reload function is on, the value set in SAR returns to the initially set value every
four transfers. In this example, when a transfer request is generated from the A/D converter, byte
data is read from the register at address H'04000080 in the A/D converter, and is written to
external memory address H'00400000. Since longword data has been transferred, the values in
SAR and DAR are H'04000084 and H'003FFFFC, respectively. The bus is kept and data transfers
are performed successively because this transfer is in burst mode.

After four transfers end, fifth and sixth transfers are performed if the address reload function is off,
and the value in SAR is incremented from H'0400008C to H'04000090, H'04000094

…

 If the

address reload function is on, DMA transfer stops after the fourth transfer ends, and the bus
request signal to the CPU is cleared.  At this time, the value stored in SAR is not incremented
from H'0400008C to H'04000090, but returns to the initially set value, H'04000080. The value in
DAR continues to be decremented regardless of whether the address reload function is on or off.