Renesas SH7709S Manual De Usuario
Rev. 5.0, 09/03, page ix of xliv
List of Items Revised or Added for This Version
Section
Page
Description
1.2 Block Diagram
Figure 1.1 Block
Diagram
Diagram
6
ASERAM deleted from figure
BRIDGE
External bus
interface
UDI
INTC
CPG/WDT
I bus 2
ASERAM deleted from legend
2.5.1 Processor States
53
Description amended
In the power-on reset state, the internal states of the CPU and the
on-chip supporting module registers are initialized. In the manual
reset state, the internal states of the CPU and registers of on-chip
supporting modules other than the bus state controller (BSC) are
initialized. Refer to
the register configurations in the relevant sections for further
details.
on-chip supporting module registers are initialized. In the manual
reset state, the internal states of the CPU and registers of on-chip
supporting modules other than the bus state controller (BSC) are
initialized. Refer to
the register configurations in the relevant sections for further
details.
5.4 Memory-Mapped
Cache
Cache
5.4.1 Address Array
113
Description amended
This operation is used to invalidate the address specification for a
cache. Write back will take place when the U bit of the entry that
received a hit is 1. Note that, when a 0 is written to the V bit, a 0
should always be written to the U bit of the same entry, too.
cache. Write back will take place when the U bit of the entry that
received a hit is 1. Note that, when a 0 is written to the V bit, a 0
should always be written to the U bit of the same entry, too.