Philips S1D13505 Manual De Usuario
Epson Research and Development
Page 147
Vancouver Design Center
Hardware Functional Specification
S1D13505
Issue Date: 01/02/02
X23A-A-001-14
15 Power Save Modes
Three power save modes are incorporated into the S1D13505 to meet the important need for power
reduction in the hand-held device market.
reduction in the hand-held device market.
1.
Refresh method is selectable by REG[1Ah]. Supported methods are CBR refresh, self-refresh
or no refresh at all.
or no refresh at all.
2.
The FPFRAME and FPLINE signals are set to their inactive states during power-down. The in-
active states are determined by REG[07h] bit 6 and REG[0Ch] bit 6. A problem may occur if
the inactive state is high (typical TFT/D-TFD configuration) and power is removed from the
LCD panel.
active states are determined by REG[07h] bit 6 and REG[0Ch] bit 6. A problem may occur if
the inactive state is high (typical TFT/D-TFD configuration) and power is removed from the
LCD panel.
For software suspend the problem can be solved in the following manner. At power-down, first
enable software suspend, then wait ~120 VNDP, and lastly reverse the polarity bits. At power-
up, first disable software suspend, then revert the polarity bits back to the configuration state.
enable software suspend, then wait ~120 VNDP, and lastly reverse the polarity bits. At power-
up, first disable software suspend, then revert the polarity bits back to the configuration state.
For hardware suspend an external hardware solution would be to use an AND gate on the sync
signal. One input of the AND gate is connected to a sync signal, the other input would be tied
to the panel’s logic power supply. When the panel’s logic power supply is removed, the sync
signal is forced low.
signal. One input of the AND gate is connected to a sync signal, the other input would be tied
to the panel’s logic power supply. When the panel’s logic power supply is removed, the sync
signal is forced low.
Table 15-1: Power Save Mode Function Summary
Function
Power Save Mode (PSM)
Normal
(Active)
No Display
LCDEnable = 0
CRTEnable = 0
CRTEnable = 0
Software
Suspend
Suspend
Hardware
Suspend
Display Active?
Yes
No
No
No
Register Access Possible?
Yes
Yes
Yes
No
Memory Access Possible?
Yes
Yes
No
No
LUT Access Possible?
Yes
Yes
Yes
No
Table 15-2: Pin States in Power-save Modes
Pins
Pin State
Normal
(Active)
No Display
LCDEnable = 0
CRTEnable = 0
CRTEnable = 0
Software
Suspend
Suspend
Hardware
Suspend
LCD outputs
Active
(LCDEnable = 1)
Forced Low
2
Forced Low
2
Forced Low
2
LCDPWR
On
(LCDEnable = 1)
Off
Off
Off
DRAM outputs
Active
CBR Refresh
only
Refresh Only
1
Refresh Only
1
CRT/DAC outputs
Active
(CRTEnable = 1)
Disabled
Disabled
Disabled
Host Interface outputs
Active
Active
Active
Disabled