Philips S1D13505 Manual De Usuario
Page 20
Epson Research and Development
Vancouver Design Center
S1D13505
Hardware Functional Specification
X23A-A-001-14
Issue Date: 01/02/02
4 Internal Description
4.1 Block Diagram Showing Datapaths
4.2 Block Descriptions
4.2.1 Register
The Register block contains all the register latches
4.2.2 Host Interface
The Host Interface (I/F) block provides the means for the CPU/MPU to communicate with the
display buffer and internal registers via one of the supported bus interfaces.
display buffer and internal registers via one of the supported bus interfaces.
4.2.3 CPU R/W
The CPU R/W block synchronizes the CPU requests for display buffer access. If SwivelView is
enabled, the data is rotated in this block.
enabled, the data is rotated in this block.
Clocks
LCD
Memory
Controller
Controller
16-bit FPM/EDO-DRAM
LCD
Power Save
Register
CRTC
Look-
I/F
CPU/MPU
Host
I/F
CPU
R/W
Display
FIFO
CRT
Cursor
FIFO
Up
Tables
Tables
DAC