Philips S1D13505 Manual De Usuario
Epson Research and Development
Page 45
Vancouver Design Center
Hardware Functional Specification
S1D13505
Issue Date: 01/02/02
X23A-A-001-14
1.
If the S1D13505 host interface is disabled, the timing for WAIT# driven is relative to the fall-
ing edge of CSn# or the first positive edge of CKIO after A[20:0], M/R# becomes valid,
whichever one is later.
ing edge of CSn# or the first positive edge of CKIO after A[20:0], M/R# becomes valid,
whichever one is later.
2.
If the S1D13505 host interface is disabled, the timing for D[15:0] driven is relative to the fall-
ing edge of RD# or the first positive edge of CKIO after A[20:0], M/R# becomes valid,
whichever one is later.
ing edge of RD# or the first positive edge of CKIO after A[20:0], M/R# becomes valid,
whichever one is later.
Table 7-2: SH-3 Timing
3.0V
a
a
Two Software WAIT States Required
5.0V
b
b
One Software WAIT State Required
Symbol
Parameter
Min
Max
Min
Max
Units
t1
Clock period
15.1
15.1
ns
t2
Clock pulse width high
6
6
ns
t3
Clock pulse width low
6
6
ns
t4
A[20:0], M/R#, RD/WR# setup to CKIO
3
3
ns
t5
A[20:0], M/R#, RD/WR# hold from CS#
0
0
ns
t6
BS# setup
4
4
ns
t7
BS# hold
1
1
ns
t8
CSn# setup
4
4
ns
t9
2
Falling edge RD# to D[15:0] driven
0
0
ns
t10
Rising edge CSn# to WAIT# tri-state
5
25
2.5
10
ns
t11
1
Falling edge CSn# to WAIT# driven
0
15
0
10
ns
t12
CKIO to WAIT# delay
4
20 3.6
12
ns
t13
D[15:0] setup to 2
nd
CKIO after BS# (write cycle)
10
10
ns
t14
D[15:0] hold (write cycle)
0
0
ns
t15
D[15:0] valid to WAIT# rising edge (read cycle)
0
0
ns
t16
Rising edge RD# to D[15:0] tri-state (read cycle)
5
25
2.5
10
ns