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Philips S1D13505 Manual De Usuario

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Epson Research and Development
Vancouver Design Center
S1D13505
Hardware Functional Specification
X23A-A-001-14
Issue Date: 01/02/02
7.5.3   4-Bit Single Color Passive LCD Panel Timing
Figure 7-28: 4-Bit Single Color Passive LCD Panel Timing
VDP 
= Vertical Display Period 
= (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1
VNDP 
= Vertical Non-Display Period 
= (REG[0Ah] bits [5:0]) + 1
HDP 
= Horizontal Display Period 
= ((REG[04h] bits [6:0]) + 1)*8Ts
HNDP  = Horizontal Non-Display Period 
= ((REG[05h] bits [4:0]) + 1)*8Ts
FPLINE
UD[3:0]
FPFRAME
FPLINE
MOD
UD2
UD1
UD0
UD3
MOD
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
FPSHIFT
VDP
LINE1
LINE2
LINE3
LINE4
LINE479 LINE480
LINE1
LINE2
VNDP
1-R1
1-G1
1-B1
1-R2
1-G2
1-B2
1-R3
1-G3
1-B3
1-R4
1-G4
1-B4
1-B319
1-R320
1-G320
1-B320
HDP
HNDP