Intel 845 Manual De Usuario
Functional Description
R
Intel
®
82845 MCH for SDR Datasheet 113
Table 15. AGP Commands Supported by the Intel
®
MCH When Acting as an AGP Target
MCH Host Bridge
AGP
Command
C/BE[3:0]#
Encoding
Cycle Destination
Response as PCIx Target
Read
0000
System memory
Low-priority read
0000
Hub interface
Complete with random data
Hi-Priority Read
0001
System memory
High-priority read
0000
The Hub interface
Complete with random data
Reserved 0010
N/A
No
response
Reserved 0011
N/A
No
response
Write
0100
System memory
Low-priority write
0100
Hub interface
Cycle goes to DRAM with byte
enables inactive
enables inactive
Hi-Priority Write
0101
System memory
High-priority write
0101
Hub interface
Cycle goes to DRAM with byte
enables inactive; does not go to
the hub interface
enables inactive; does not go to
the hub interface
Reserved 0110
N/A
No
response
Reserved 0111
N/A
No
response
Long Read
1000
System memory
Low-priority read
Hub interface
Complete locally with random data;
does not go to the hub interface
does not go to the hub interface
Hi-Priority Long
Read
Read
1001 System
memory
High-priority
read
Hub interface
Complete with random data
Flush
1010
MCH
Complete with QW of random data
Reserved 1011
N/A
No
response
Fence
1100
MCH
No response; Flag inserted in
MCH request queue
MCH request queue
Reserved 1101
N/A
No
response
Reserved 1110
N/A
No
response
Reserved 1111
N/A
No
response
NOTES:
1. N/A refers to a function that is not applicable
As a target of an AGP cycle, the MCH supports all the transactions targeting system memory
(summarized in Table 15). The MCH supports both normal and high-priority read and write
requests. The MCH does not support AGP cycles to the hub interface. PIPE# and SBA cycles do
not require coherency management and all AGP initiator accesses to system memory, using AGP
PIPE# or SBA protocol, are treated as non-snoopable cycles. These accesses are directed to the
AGP aperture in system memory that is programmed as either uncacheable (UC) memory or write
combining (WC) in the processor’s MTRRs.
(summarized in Table 15). The MCH supports both normal and high-priority read and write
requests. The MCH does not support AGP cycles to the hub interface. PIPE# and SBA cycles do
not require coherency management and all AGP initiator accesses to system memory, using AGP
PIPE# or SBA protocol, are treated as non-snoopable cycles. These accesses are directed to the
AGP aperture in system memory that is programmed as either uncacheable (UC) memory or write
combining (WC) in the processor’s MTRRs.