Emerson PMPPC7448 Manual De Usuario
System Controller:
66 MHz Bus Operation
5-14
66 MHZ BUS OPERATION
Conventional PCI:
In order for the PCI bus to operate at 66 MHz, all devices on the bus must be capable of that
speed. When the M66EN signal (connector P12 pin 47) is high for a particular PCI device, it
indicates that the device can operate at 66 MHz. For 33 MHz modules, M66EN is grounded,
so the signal will be high only when all devices on the PCI bus are capable of operating at 66
MHz. Software can read bit 21 of the PCI Status and Command register to determine the
bus speed. If bit 21 is high, the bus speed is 66 MHz; if it is low, the bus speed is 33 MHz. If
any PCI device pulls the wire or M66EN signal low, then the bus speed will be 33 MHz for all
of the devices. Please see the PPMC standard (reference in
speed. When the M66EN signal (connector P12 pin 47) is high for a particular PCI device, it
indicates that the device can operate at 66 MHz. For 33 MHz modules, M66EN is grounded,
so the signal will be high only when all devices on the PCI bus are capable of operating at 66
MHz. Software can read bit 21 of the PCI Status and Command register to determine the
bus speed. If bit 21 is high, the bus speed is 66 MHz; if it is low, the bus speed is 33 MHz. If
any PCI device pulls the wire or M66EN signal low, then the bus speed will be 33 MHz for all
of the devices. Please see the PPMC standard (reference in
) for carrier board pull-
up requirements.
WATCHDOG TIMER
The 32-bit count down watchdog timer generates a nonmaskable interrupt or resets the
system in the event of unpredictable software behavior. After the watchdog is enabled, it is
a free-running counter that requires periodic servicing to prevent its expiration. After reset,
the watchdog is disabled.
system in the event of unpredictable software behavior. After the watchdog is enabled, it is
a free-running counter that requires periodic servicing to prevent its expiration. After reset,
the watchdog is disabled.
RESET
Circuitry on the PmPPC7448 resets the entire module if the voltages fall out of tolerance
(due to power-on reset) or if the optional on-board reset switch is activated. The Marvell
MV64460 control register settings are initialized immediately following this reset to config-
ure the module properly before allowing any external PCI accesses to occur. The MV64460
supports three reset pins:
(due to power-on reset) or if the optional on-board reset switch is activated. The Marvell
MV64460 control register settings are initialized immediately following this reset to config-
ure the module properly before allowing any external PCI accesses to occur. The MV64460
supports three reset pins:
SYSRST*:
SYSRST* is the main reset pin. When asserted, all MV64460 logics are in a reset state and all
outputs are floated, except for DRAM address and control outputs. SYSRST* is separated
from the PCI reset pins so the CPU can boot and start to initialize the board before the PCI
slot reset signal is deasserted.
outputs are floated, except for DRAM address and control outputs. SYSRST* is separated
from the PCI reset pins so the CPU can boot and start to initialize the board before the PCI
slot reset signal is deasserted.
PCI0_RST* and PCI1_RST*:
These pins are the independent PCI interface reset pins. The PCI is kept in a reset state as
long as its corresponding reset pin is asserted. On reset deassertion, all PCI configuration
registers are set to their initial values as specified in the PCI specification. The two methods
of PCI reset configuration include: pins sampled on SYSRST* deassertion and serial ROM ini-
tialization. Only PCI0 is functional on the PmPPC7448.
registers are set to their initial values as specified in the PCI specification. The two methods
of PCI reset configuration include: pins sampled on SYSRST* deassertion and serial ROM ini-
tialization. Only PCI0 is functional on the PmPPC7448.
Caution:
When the MV64460 is in reset, any other attempts for PCI device access is ignored.
Therefore, use RESET_OUT and drive RST as long as it is asserted or wait for EReady
assertion before attempting an access.
Therefore, use RESET_OUT and drive RST as long as it is asserted or wait for EReady
assertion before attempting an access.
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