Emerson PMPPC7448 Manual De Usuario
CPLD:
Reset Registers
7-2
Register 7-2:
Reset Command Register (RCR) at 0xf820,1000
SCL:
Serial I
2
C Clock
1 Tri-states the PLD
0 Drives logic low
0 Drives logic low
SDA:
Serial I
2
C Data/Address
1 Tri-states the PLD
0 Drives logic low
0 Drives logic low
R:
Reserved (default is 00)
I2C:
I
2
C reset
1 Causes the I
2
C bus to be reset into a known state
0 No I
2
C reset (default)
FR:
Flash Reset command
1 Causes Flash to be reset
0 No Flash reset (default)
1 Causes Flash to be reset
0 No Flash reset (default)
SR:
Soft Reset command
1 Causes a soft reset to the CPU and resets on-board Flash
0 No soft reset (default)
1 Causes a soft reset to the CPU and resets on-board Flash
0 No soft reset (default)
HR:
Hard Reset command
1 Causes a hard reset on board
0 No hard reset (default)
1 Causes a hard reset on board
0 No hard reset (default)
PCI Reset Out Enable Register (ROER)
The Reset Out Enable register determines the functionality of the PCI ResetOut signal.
Register 7-3:
Reset Out Enable Register (ROER) at 0xf820,e000
R:
Reserved (default is 00)
7
6
5
4
3
2
1
0
SCL
SDA
R
I2C
FR
SR
R
HR
7
6
5
4
3
2
1
0
R
SW
WD
R
COPH
R
PCI0
FP