Emerson PMPPC7448 Manual De Usuario

 I2C Interface

PmPPC7448 User’s Manual

A baud tuning mechanism adjusts the generated clock rate to the receive clock rate. When 
baud tuning is enabled, the baud tuning mechanism monitors for a start bit (for example 
high-to-low transition). Once the start bit is found, the baud tuning machine measures the 
bit length by counting up until the next Low-to-High transition. Then the count-up value of 
the BRG is loaded into the Count Up Value (CUV) register and a maskable interrupt is gener-
ated signaling the CPU that the bit length value is available. Finally, the CPU reads the value 
from the CUV and adjusts the CDV to the requested value.

The MV64460 has full I

2

C interface support, acting as both a master generating read/write 

requests and as a slave responding to read/write requests. The I

2

C port consists of two 

open drain signals—serial clock (SCL) and serial data/address (SDA).

Note:

An I

2

C serial configuration ROM is connected to the MV64460’s I

2

C interface, and is dis-

abled by default. Emerson uses the addresses in 

 for I

2

C devices.

Table 8-1:

Specific PmPPC7448 configurations provide a standard EIA-232 serial I/O port; P2 is a mini-
USB connector available at the front panel. See 

 below. The cable wiring assign-

ments are in 

Figure 8-1:

64460 I

2

C (U33)

0xA4

NVRAM I

2

C (U34)

0xA6

RTC (U36)

0xD0

SO-DIMM I2C (U3)

0xAE

Pin 1