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Emerson PMPPC7448 Manual De Usuario

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Development Mezzanine Card:
 PmPPC7448 to DMC JTAG
10-7
PMPPC7448 TO DMC JTAG
Figure 10-4:
PmPPC7448 to DMC JTAG Block Diagram
P3 JTAG/COP
The JTAG/COP interface provides for boundary-scan testing of the CPU and the 
PmPPC7448. This interface is compliant with the IEEE 1149.1 standard.
Figure 10-5:
DMC P3 JTAG/COP Header
MPC7448
Device
CPLD
Development
Mezzanine Card
(DMC)
COP Debug
TDO
TDI
TCK
TMS
TRST*
15
16
2
PLD JTAG
TCK
TDO
TMS
10
2
TDI
CPLD_TDI
CPLD_TMS
CPLD_TDO
CPLD_TCK
MPC7448_TDO
MPC7448_TDI
MPC7448_TCK
MPC7448_TMS
MPC7448_SRESET*
MPC7448_HRESET*
MPC7448_TRST*
MPC7448_SRESET_OUT*
MPC7448_HRESET_OUT*
MPC7448_TRST_OUT*
DEBUG_TRST*
DEBUG_TRST_B*
DEBUG_HRESET_B*
DEBUG_SRESET_B*
CPLD
TCK
TDO
TMS
TDI
TCK
TDI
TDO
TMS
CKSTP_OUT*
SRESET*
HRESET*
TRST*
MPC7448_CKSTP_OUT*
DEBUG_SRESET*
DEBUG_HRESET*
DMC Connector
Convert
3.3 V    1.8V
Convert
1.8 V    3.3V
1
2
15
16