Intel 413808 Manual De Usuario

Intel

413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

203

Address Translation Unit (PCI-X)—Intel

413808 and 413812

PIE:

Pending Insertion/Extraction

This status bit is set and cleared by the 4138xx Hot-Swap state Machine.

When 1b this bit indicates that either an insertion or an extraction is in progress (either INS or EXT

has a value of 1b or INS is armed).

EIM:

ENUM# Interrupt Mask.

When 0b:

4138xx asserts P_ENUM# when an insertion or removal event occurs as indicated by the setting of

the INS or EXT bits of this register.

When 1b:

4138xx does not assert P_ENUM# under any circumstances.

DHA:

Device Hiding Armed:

When 1b:

When

HS_SM#

= 0b, and LSTAT = 1b (Switch open) and the LOO bit = 1b, 4138xx completes any

bus cycles presently in process and then cease to initiate or respond to either primary or secondary

bus cycles. When LSTAT subsequently goes low, 4138xx responds normally to bus cycles.

When 0:

4138xx operates normally.

Table 90. HS_CNTRL - Hot-Swap Control/Status Register (Sheet 2 of 2)

Bit

Default

Description

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

RW = Read/Write

RO = Read Only

RT = Read/Toggle

RC = Read/Clear

SW = SROM Write

NA = Not Accessible

+0EAH