Intel 413808 Manual De Usuario

Intel

413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

Introduction—Intel

413808 and 413812

The overall high-level architecture is shown in

Figure 1

When the 4138xx is in TPER mode, the interface to the host driver is under the control

of the Application Core, and as with the 81348, the MU provides the hardware for the

messaging interface. Note however, that since there is no DDR2 the MU is unable to

make use of the Index Registers or Circular Queues, since these rely upon DDR2.

However, the rest of the MU functionality is available.
The interface between the Application Core and the Transport Core continues to be SLI

with the support of the TPMI registers. The Application Core is assigned a total of

256KB of SRAM for its use. The SLI IOCB Command and Response Rings and the SLI

Port Pointers must reside in SRAM instead of DDR2. This comes out of the 256KB region

assigned to the Application Core as specified by the PCB structure as communicated by

the SLI Configuration Port (CONFIG_SLI_PORT) command. Complete details on the

Application Core section of SRAM, including alignment requirements, addresses, etc.,

can be found in the SCDL Architecture Specification, Firmware Release Notes, Sample

Code which is included in the Software Developer’s Kit package.
The following is a list of other features, both silicon and firmware that are not available

with the TPER usage model.

• 4138xx in TPER mode (when using 81348 silicon these features are available):

—

ADMA

—

MU circular queues, index registers.

• TPER Transport Firmware (differences from 81348 1.0 firmware features):

—

CONFIG_SAS_GPIO is not available when running TPER firmware.

—

Fewer addressable targets and outstanding I/Os supported, refer to the firmware release
notes for the version in question for specifics.

—

Ring memory and port pointers allocated from application core SRAM region.

—

Any application core host messaging interface memory required allocated from application
core SRAM.

Figure 1.

TPER Architecture Overview

SLI Host PTRs

SLIM (BAR 0)

SLI CMD Wings

SLI RSP Wings

SLI PORT PTRs

Application Core Memory

Transport Memory

SRAM

Driver

TPMI

Application

Core

Transport

Core