Intel 413808 Manual De Usuario

Intel

413808 and 413812—SRAM DMA Unit (SDMA)

Intel

413808 and 413812 I/O Controllers in TPER Mode

Developer’s Manual

October 2007

456

Order Number: 317805-001US

5.4.13

HostToLocal Control/Status Register - H2L_CSR

The HostToLocal Control/Status Register (H2L_CSR) provides the status and control of

the HostToLocal channel.

Table 311. HostToLocal Control/Status Register - H2L_CSR

Bit

Default

Description

31:27

00000

Reserved

26:24

000

Error Flags - Read/Clear

One or more of these bits is set to indicate an error has occurred with the DMA operation. The precise

cause of the error is determined by reading the ATU or XSISC error registers.

23:02

0000H

Reserved

Channel Go (CHGO) - Read/Set

Set this bit to begin the DMA operation.

This bit must be cleared while the DMA registers are being set up. The CHGO bit is set by firmware to

begin the DMA operation. When the DMA operation begins the hardware clears this bit. Note that

clearing of this bit does not indicate the DMA operation is complete, rather that the hardware has

started processing it.

Enable Register - Read/Write

Must be set for proper operation. A value of zero (when the CHGO bit is set) has unpredictable results.

Coprocessor

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Internal bus address offset

1828CH