Cypress CY7C1541V18 Manual De Usuario
CY7C1541V18, CY7C1556V18
CY7C1543V18, CY7C1545V18
CY7C1543V18, CY7C1545V18
Document Number: 001-05389 Rev. *F
Page 24 of 28
Switching Waveforms
Read/Write/Deselect Sequence
Figure 5. Waveform for 2.0 Cycle Read Latency
tKH
tKL
tCYC
tKHKH
NOP
READ
NOP
WRITE
READ
WRITE
1
2
3
4
5
6
7
8
t
t
t
tSA HA
SC
HC
tHD
tSC tHC
A0
A1
A2
A3
t
t
SD
HD
t SD
D11
D10
D12
D13
D30
D31
D32
D33
D
A
WPS
RPS
K
K
DON’T CARE
UNDEFINED
CQ
CQ
tCQOH
CCQO
t
tCQOH
CCQO
t
tQVLD
QVLD
tQVLD
(Read Latency = 2.0 Cycles)
CLZ
t
t
CO
tDOH
tCQDOH
CQD
t
tCHZ
Q00
Q01
Q20
Q02
Q21
Q03
Q22
Q23
tCQH
t
CQHCQH
Q
Notes
31. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.
32. Outputs are disabled (High-Z) one clock cycle after a NOP.
33. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwarded immediately as read results. This note
32. Outputs are disabled (High-Z) one clock cycle after a NOP.
33. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwarded immediately as read results. This note
applies to the whole diagram.