Cypress CY7C1527JV18 Manual De Usuario
CY7C1516JV18, CY7C1527JV18
CY7C1518JV18, CY7C1520JV18
CY7C1518JV18, CY7C1520JV18
Document Number: 001-12559 Rev. *D
Page 2 of 26
Logic Block Diagram (CY7C1516JV18)
Logic Block Diagram (CY7C1527JV18)
Write
Reg
Reg
Write
Reg
Reg
CLK
A
(21:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add
. Decode
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
8
16
8
NWS
[1:0]
V
REF
W
rite Add. Decode
8
22
C
C
8
LD
Control
R/W
DOFF
4M x 8 Arra
y
4M
x
8
A
rr
rr
a
y
8
DQ
[7:0]
8
CQ
CQ
Write
Reg
Reg
Write
Reg
Reg
CLK
A
(21:0)
Gen.
K
K
Control
Logic
Address
Register
Read
A
d
d. Decode
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
9
18
9
BWS
[0]
V
REF
W
rite Add. Decode
9
22
C
C
9
LD
Control
R/W
DOFF
4M x 9 Arr
a
y
4M x 9 A
rray
9
DQ
[8:0]
9
CQ
CQ