Cypress CY7C604XX Manual De Usuario
CY7C604XX
Document Number: 001-12395 Rev *H
Page 24 of 30
AC I
2
C Specifications
Figure 8. Definition of Timing for Fast/Standard Mode on the I
2
C Bus
Table 20. AC Characteristics of the I
2
C SDA and SCL Pins
Symbol
Description
Standard Mode
Fast Mode
Units
Min
Max
Min
Max
F
SCLI2C
SCL Clock Frequency
0
100
0
400
kHz
T
HDSTAI2C
Hold Time (repeated) START Condition. After this period,
the first clock pulse is generated.
the first clock pulse is generated.
4.0
–
0.6
–
μs
T
LOWI2C
LOW Period of the SCL Clock
4.7
–
1.3
–
μs
T
HIGHI2C
HIGH Period of the SCL Clock
4.0
–
0.6
–
μs
T
SUSTAI2C
Setup Time for a Repeated START Condition
4.7
–
0.6
–
μs
T
HDDATI2C
Data Hold Time
0
–
0
–
μs
T
SUDATI2C
Data Setup Time
250
–
100
–
ns
T
SUSTOI2C
Setup Time for STOP Condition
4.0
–
0.6
–
μs
T
BUFI2C
Bus Free Time Between a STOP and START Condition
4.7
–
1.3
–
μs
T
SPI2C
Pulse Width of Spikes are Suppressed by the Input Filter
–
–
0
50
ns
SDA
SCL
S
Sr
S
P
T
BUFI2C
T
SPI2C
T
HDSTAI2C
T
SUSTOI2C
T
SUSTAI2C
T
LOWI2C
T
HIGHI2C
T
HDDATI2C
T
HDSTAI2C
T
SUDATI2C
Notes
22. A fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement t
SU;DAT
Š 250 ns must then be met. This is automatically the case
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line t
SDA line t
rmax
+ t
SU;DAT
= 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before the SCL line is released.