Cypress CY7C1471BV33 Manual De Usuario
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Document #: 001-15029 Rev. *B
Page 18 of 32
TAP Timing
Figure 3. TAP Timing
TAP AC Switching Characteristics
Over the Operating Range
Parameter
Description
Min
Max
Unit
Clock
t
TCYC
TCK Clock Cycle Time
50
ns
t
TF
TCK Clock Frequency
20
MHz
t
TH
TCK Clock HIGH time
20
ns
t
TL
TCK Clock LOW time
20
ns
Output Times
t
TDOV
TCK Clock LOW to TDO Valid
5
ns
t
TDOX
TCK Clock LOW to TDO Invalid
0
ns
Setup Times
t
TMSS
TMS Setup to TCK Clock Rise
5
ns
t
TDIS
TDI Setup to TCK Clock Rise
5
ns
t
CS
Capture Setup to TCK Rise
5
ns
Hold Times
t
TMSH
TMS Hold after TCK Clock Rise
5
ns
t
TDIH
TDI Hold after Clock Rise
5
ns
t
CH
Capture Hold after Clock Rise
5
ns
t
TL
Test Clock
(TCK )
1
2
3
4
5
6
Test M ode Select
(TM S)
tTH
Test Data-O ut
(TDO )
tCYC
Test Data-In
(TDI)
tTM SH
tTM SS
tTDIH
tTDIS
tTDOX
tTDOV
DO N’T CA RE
UNDEFINED
Notes
10.t
CS
and t
CH
refer to the setup and hold time requirements of latching data from the boundary scan register.
11.Test conditions are specified using the load in TAP AC Test Conditions. t
R
/t
F
= 1 ns.