Cypress CY7C1471BV33 Manual De Usuario

Document #: 001-15029 Rev. *B

Page 8 of 32

A

0

, A

1

, A

Input-

Synchronous

Address Inputs used to select one of the Address Locations. Sampled at the rising edge 
of the CLK. A

[1:0]

 is fed to the two-bit burst counter.

BW

A

, BW

B

, 

BW

C

, BW

D

,

BW

E

, BW

F

,

BW

G

, BW

H

Input-

Synchronous

Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled 
on the rising edge of CLK.

WE

Input-

Synchronous

Write Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW. 
This signal must be asserted LOW to initiate a write sequence.

ADV/LD

Input-

Synchronous

Advance/Load Input. Advances the on-chip address counter or loads a new address. When 
HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new 
address can be loaded into the device for an access. After deselection, drive ADV/LD LOW to 
load a new address.

CLK

Input-
Clock

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. 
CLK is only recognized if CEN is active LOW.

CE

1

Input-

Synchronous

Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction 
with CE

2

 and CE

3

 to select or deselect the device.

CE

2

Input-

Synchronous

Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction 
with CE

1 

and CE

3

 to select or deselect the device. 

CE

3

Input-

Synchronous

Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction 
with CE

1

 and

 

CE

2 

to select or deselect the device.

OE

Input-

Asynchronous

Output Enable, Asynchronous Input, Active LOW. Combined with the synchronous logic 
block inside the device to control the direction of the IO pins. When LOW, the IO pins are enabled 
to behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. 
OE is masked during the data portion of a write sequence, during the first clock when emerging 
from a deselected state, and when the device is deselected. 

CEN

Input-

Synchronous

Clock Enable Input, Active LOW. When asserted LOW the clock signal is recognized by the 
SRAM. When deasserted HIGH the clock signal is masked. Because deasserting CEN does 
not deselect the device, CEN can be used to extend the previous cycle when required.

ZZ

Input-

Asynchronous

ZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep” 
condition with data integrity preserved. During normal operation, this pin must be LOW or left 
floating. ZZ pin has an internal pull down.

DQ

s

IO-

Synchronous

Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered 
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location 
specified by the addresses presented during the previous clock rise of the read cycle. The 
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. 
When HIGH, DQ

s

 and DQP

X

 are placed in a tri-state condition.The outputs are automatically 

tri-stated during the data portion of a write sequence, during the first clock when emerging from 
a deselected state, and when the device is deselected, regardless of the state of OE.

DQP

X

IO-

Synchronous

Bidirectional Data Parity IO Lines. Functionally, these signals are identical to DQ

s

.

 

During 

write sequences, DQP

X

 is controlled by BW

X

 correspondingly.

MODE

Input Strap Pin

Mode Input. Selects the Burst Order of the Device. When tied to Gnd selects linear burst 
sequence. When tied to V

DD

 or left floating selects interleaved burst sequence.

V

DD

Power Supply 

Power Supply Inputs to the Core of the Device. 

V

DDQ

IO Power Supply Power Supply for the IO Circuitry. 

V

SS

Ground

Ground for the Device.