Cypress CY7C1474V25 Manual De Usuario
CY7C1470V25
CY7C1472V25
CY7C1474V25
CY7C1472V25
CY7C1474V25
Document #: 38-05290 Rev. *I
Page 28 of 28
*I
472335
See ECN
VKN
Corrected the typo in the pin configuration for 209-Ball FBGA pinout
(Corrected the ball name for H9 to V
(Corrected the ball name for H9 to V
SS
from V
SSQ
).
Added the Maximum Rating for Supply Voltage on V
DDQ
Relative to GND.
Changed t
TH
, t
TL
from 25 ns to 20 ns and t
TDOV
from 5 ns to 10 ns in TAP AC
Switching Characteristics table.
Updated the Ordering Information table.
Updated the Ordering Information table.
Document Title: CY7C1470V25/CY7C1472V25/CY7C1474V25 72-Mbit(2M x 36/4M x 18/1M x 72)
Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05290
Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05290