Cypress CY7C68013A Manual De Usuario
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
CY7C68015A, CY7C68016A
Document #: 38-08032 Rev. *L
Page 38 of 62
10.2 Program Memory Read
Figure 12. Program Memory Read Timing Diagram
t
CL
t
DH
t
SOEL
t
SCSL
PSEN#
D[7..0]
OE#
A[15..0]
CS#
t
STBL
data in
t
ACC1
t
AV
t
STBH
t
AV
CLKOUT
Table 15. Program Memory Read Parameters
Parameter
Description
Min
Typ
Max
Unit
Notes
t
CL
1/CLKOUT Frequency
20.83
ns
48 MHz
41.66
ns
24 MHz
83.2
ns
12 MHz
t
AV
Delay from Clock to Valid Address
0
10.7
ns
t
STBL
Clock to PSEN Low
0
8
ns
t
STBH
Clock to PSEN High
0
8
ns
t
SOEL
Clock to OE Low
11.1
ns
t
SCSL
Clock to CS Low
13
ns
t
DSU
Data Setup to Clock
9.6
ns
t
DH
Data Hold Time
0
ns
Notes
17. CLKOUT is shown with positive polarity.
18. t
18. t
ACC1
is computed from the above parameters as follows:
t
ACC1
(24 MHz) = 3*t
CL
– t
AV
– t
DSU
= 106 ns
t
ACC1
(48 MHz) = 3*t
CL
– t
AV
– t
DSU
= 43 ns.