Cypress CY7C68014A Manual De Usuario

Document #: 38-08032 Rev. *L

Page 3 of 62

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Portable video recorder

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MPEG/TV conversion

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DSL modems

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ATA interface

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Memory card readers

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Legacy conversion devices

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Cameras

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Scanners

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Home PNA

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Wireless LAN

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MP3 players

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Networking

The “Reference Designs” section of the 

provides additional tools for typical USB 2.0 applications. Each
reference design comes complete with firmware source and
object code, schematics, and documentation. Visit the 

 for more information.

FX2LP operates at two of the three rates defined in the USB
Specification Revision 2.0, dated April 27, 2000:

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Full-speed, with a signaling bit rate of 12 Mbps

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High-speed, with a signaling bit rate of 480 Mbps.

FX2LP does not support the low speed signaling mode of
1.5 Mbps.

The 8051 microprocessor embedded in the FX2LP family has
256 bytes of register RAM, an expanded interrupt system, three
timer/counters, and two USARTs.

FX2LP has an on-chip oscillator circuit that uses an external 24
MHz (±100 ppm) crystal with the following characteristics:

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Parallel resonant

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Fundamental mode

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500-

μW drive level

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12-pF (5% tolerance) load capacitors

An on-chip PLL multiplies the 24 MHz oscillator up to 480 MHz,
as required by the transceiver/PHY and internal counters divide
it down for use as the 8051 clock. The default 8051 clock

frequency is 12 MHz. The clock frequency of the 8051 can be
changed by the 8051 through the CPUCS register, dynamically.

The CLKOUT pin, which can be three-stated and inverted using
internal control bits, outputs the 50% duty cycle 8051 clock, at
the selected 8051 clock frequency: 48 MHz, 24 MHz, or 12 MHz.

FX2LP contains two standard 8051 USARTs, addressed via
Special Function Register (SFR) bits. The USART interface pins
are available on separate IO pins, and are not multiplexed with
port pins. 

UART0 and UART1 can operate using an internal clock at
230 KBaud with no more than 1% baud rate error. 230 KBaud
operation is achieved by an internally derived clock source that
generates overflow pulses at the appropriate time. The internal
clock adjusts for the 8051 clock rate (48 MHz, 24 MHz, and 12
MHz) such that it always presents the correct frequency for 230
KBaud operation.

Certain 8051 SFR addresses are populated to provide fast
access to critical FX2LP functions. These SFR additions are
shown in 

 on page 4. Bold type indicates non standard,

enhanced 8051 registers. The two SFR rows that end with “0”
and “8” contain bit addressable registers. The four IO ports A to
D use the SFR addresses used in the standard 8051 for ports 0
to 3, which are not implemented in FX2LP. Because of the faster
and more efficient SFR addressing, the FX2LP IO ports are not
addressable in external RAM space (using the MOVX
instruction).

FX2LP supports the I

2

C bus as a master only at 100-/400- KHz.

SCL and SDA pins have open-drain outputs and hysteresis
inputs. These signals must be pulled up to 3.3V, even if no I

2

C

device is connected.

All packages, 8-bit or 16-bit “FIFO” bidirectional data bus, multi-
plexed on IO ports B and D. 128-pin package: adds 16-bit
output-only 8051 address bus, 8-bit bidirectional data bus.

12 pf

12 pf

24 MHz

20 × PLL

C1

C2

12-pF capacitor values assumes a trace capacitance

of 3 pF per side on a four-layer FR4 PCA

1. 115 KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0, UART1, or both respectively.