Cypress CY7C68014A Manual De Usuario

Document #: 38-08032 Rev. *L

Page 51 of 62

The 

 shows the timing relationship of the SLAVE FIFO

signals during a synchronous write using IFCLK as the synchro-
nizing clock. The diagram illustrates a single write followed by
burst write of 3 bytes and committing all 4 bytes as a short packet
using the PKTEND pin.

■

At t = 0 the FIFO address is stable and the signal SLCS is 
asserted. (SLCS may be tied low in some applications) Note 
that t

SFA 

has a minimum of 25 ns. This means when IFCLK is 

running at 48 MHz, the FIFO address setup time is more than 
one IFCLK cycle.

■

At t = 1, the external master/peripheral must outputs the data 
value onto the data bus with a minimum set up time of t

SFD

 

before the rising edge of IFCLK.

■

At t = 2, SLWR is asserted. The SLWR must meet the setup 
time of t

SWR

 (time from asserting the SLWR signal to the rising 

edge of IFCLK) and maintain a minimum hold time of t

WRH

 (time 

from the IFCLK edge to the deassertion of the SLWR signal). 
If the SLCS signal is used, it must be asserted with SLWR or 
before SLWR is asserted (The SLCS and SLWR signals must 
both be asserted to start a valid write condition).

■

While the SLWR is asserted, data is written to the FIFO and on 
the rising edge of the IFCLK, the FIFO pointer is incremented. 
The FIFO flag is also updated after a delay of t

XFLG

 from the 

rising edge of the clock.

The same sequence of events are also shown for a burst write
and are marked with the time indicators of T = 0 through 5. 

Note For the burst mode, SLWR and SLCS are left asserted for
the entire duration of writing all the required data values. In this
burst write mode, after the SLWR is asserted, the data on the

FIFO data bus is written to the FIFO on every rising edge of
IFCLK. The FIFO pointer is updated on each rising edge of
IFCLK. In 

, after the four bytes are written to the FIFO,

SLWR is deasserted. The short 4 byte packet can be committed
to the host by asserting the PKTEND signal. 

There is no specific timing requirement that should be met for
asserting PKTEND signal with regards to asserting the SLWR
signal. PKTEND can be asserted with the last data value or
thereafter. The only requirement is that the setup time t

SPE

 and

the hold time t

PEH

 must be met. In the scenario of 

, the

number of data values committed includes the last value written
to the FIFO. In this example, both the data value and the
PKTEND signal are clocked on the same rising edge of IFCLK.
PKTEND can also be asserted in subsequent clock cycles. The
FIFOADDR lines should be held constant during the PKTEND
assertion.

Although there are no specific timing requirement for the
PKTEND assertion, there is a specific corner case condition that
needs attention while using the PKTEND to commit a one
byte/word packet. Additional timing requirements exists when
the FIFO is configured to operate in auto mode and it is desired
to send two packets: a full packet (full defined as the number of
bytes in the FIFO meeting the level set in AUTOINLEN register)
committed automatically followed by a short one byte or word
packet committed manually using the PKTEND pin. 

In this case, the external master must ensure to assert the
PKTEND pin at least one clock cycle after the rising edge that
caused the last byte or word that needs to be clocked into the
previous auto committed packet (the packet with the number of
bytes equal to what is set in the AUTOINLEN register). Refer to

 for further details on this timing.

t=0

t=1

t=2

t=3

T=1

T=0

T=2

T=5

T=3

T=4