Cypress CY7C1916JV18 Manual De Usuario
CY7C1316JV18, CY7C1916JV18
CY7C1318JV18, CY7C1320JV18
CY7C1318JV18, CY7C1320JV18
Document Number: 001-15271 Rev. *B
Page 9 of 26
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175
Ω and 350Ω
,
with V
DDQ
= 1.5V. The
output impedance is adjusted every 1024 cycles at power up to
account for drifts in supply voltage and temperature.
account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the DDR-II to simplify data capture
on high-speed systems. Two echo clocks are generated by the
DDR-II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free running clocks and are synchro-
nized to the output clock of the DDR-II. In the single clock mode,
CQ is generated with respect to K and CQ is generated with
respect to K. The timing for the echo clocks is shown in
on high-speed systems. Two echo clocks are generated by the
DDR-II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free running clocks and are synchro-
nized to the output clock of the DDR-II. In the single clock mode,
CQ is generated with respect to K and CQ is generated with
respect to K. The timing for the echo clocks is shown in
DLL
These chips use a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. During power up, when the DOFF is tied HIGH, the
DLL is locked after 1024 cycles of stable clock. The DLL can also
be reset by slowing or stopping the input clocks K and K for a
minimum of 30 ns. However, it is not necessary for the to specif-
ically reset the DLL to lock it to the desired frequency. The DLL
automatically locks 1024 clock cycles after a stable clock is
presented. The DLL may be disabled by applying ground to the
DOFF pin. When the DLL is turned off, the device behaves in
DDR-I mode (with one cycle latency and a longer access time).
For information refer to the application note DLL Considerations
in QDRII™/DDRII.
function between 120 MHz and the specified maximum clock
frequency. During power up, when the DOFF is tied HIGH, the
DLL is locked after 1024 cycles of stable clock. The DLL can also
be reset by slowing or stopping the input clocks K and K for a
minimum of 30 ns. However, it is not necessary for the to specif-
ically reset the DLL to lock it to the desired frequency. The DLL
automatically locks 1024 clock cycles after a stable clock is
presented. The DLL may be disabled by applying ground to the
DOFF pin. When the DLL is turned off, the device behaves in
DDR-I mode (with one cycle latency and a longer access time).
For information refer to the application note DLL Considerations
in QDRII™/DDRII.
Application Example
shows two DDR-II used in an application.
Figure 1. Application Example
Vterm = 0.75V
Vterm = 0.75V
R = 50
ohms
R = 250
ohms
LD#
C C#
R/W#
DQ
A
A
K
LD#
C C#
R/W#
DQ
A
A
K
SRAM#1
SRAM#2
R
= 250ohms
BUS
MASTER
(CPU
or
ASIC)
DQ
Addresses
Cycle Start#
R/W#
Return CLK
Source CLK
Return CLK#
Source CLK#
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
Echo Clock2/Echo Clock#2
ZQ
CQ/CQ#
K#
ZQ
CQ/CQ#
K#