Cypress CY8CNP102E Manual De Usuario

Document #: 001-43991 Rev. *D

Page 21 of 38

T

RSCLK

Rise Time of SCLK 

1

–

20

ns

T

FSCLK

Fall Time of SCLK 

1

–

20

ns

T

SSCLK

Data Set up Time to Falling Edge of SCLK

40

–

–

ns

T

HSCLK

Data Hold Time from Falling Edge of SCLK

40

–

–

ns

F

SCLK

Frequency of SCLK

0

–

8

MHz

T

ERASEB

Flash Erase Time (Block)

–

10

–

ms

T

WRITE

Flash Block Write Time

–

10

–

ms

T

DSCLK3

Data Out Delay from Falling Edge of SCLK

–

–

50

ns

3.0V 

≤ Vcc ≤ 3.6V

F

SCLI2C

SCL Clock Frequency

0

100

0

400

kHz

T

HDSTAI2C

Hold Time (repeated) START Condition. After this period, the 

first clock pulse is generated.

4.0

–

0.6

–

μs

T

LOWI2C

LOW Period of the SCL Clock

4.7

–

1.3

–

μs

T

HIGHI2C

HIGH Period of the SCL Clock

4.0

–

0.6

–

μs

T

SUSTAI2C

Setup Time for a Repeated START Condition

4.7

–

0.6

–

μs

T

HDDATI2C

Data Hold Time

0

–

0

–

μs

T

SUDATI2C

Data Setup Time

250

–

100

–

ns

T

SUSTOI2C

Setup Time for STOP Condition

4.0

–

0.6

–

μs

T

BUFI2C

Bus Free Time Between a STOP and START Condition

4.7

–

1.3

–

μs

T

SPI2C

Pulse Width of spikes are suppressed by the input filter.

–

–

0

50

ns

9. A Fast Mode I2C-bus device may be used in a Standard-Mode I2C-bus system, but the requirement tSUDAT 

≥

 250 ns must then be met. This is automatically the 

case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit 

to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard Mode I2C bus specification) before the SCL line is released.