Cypress CY8CNP102E Manual De Usuario

Document #: 001-43991 Rev. *D

Page 32 of 38

T

RSCLK

Rise Time of SCLK 

1

–

20

ns

T

FSCLK

Fall Time of SCLK 

1

–

20

ns

T

SSCLK

Data Set up Time to Falling Edge of SCLK

40

–

–

ns

T

HSCLK

Data Hold Time from Falling Edge of SCLK

40

–

–

ns

F

SCLK

Frequency of SCLK

0

–

8

MHz

T

ERASEB

Flash Erase Time (Block)

–

10

–

ms

T

WRITE

Flash Block Write Time

–

10

–

ms

T

DSCLK

Data Out Delay from Falling Edge of SCLK

–

–

45

ns

4.75V 

≤ Vcc ≤ 5.25V

F

SCLI2C

SCL Clock Frequency

0

100

0

400

kHz

T

HDSTAI2C

Hold Time (repeated) START Condition. After this 

period, the first clock pulse is generated.

4.0

–

0.6

–

μs

T

LOWI2C

LOW Period of the SCL Clock

4.7

–

1.3

–

μs

T

HIGHI2C

HIGH Period of the SCL Clock

4.0

–

0.6

–

μs

T

SUSTAI2C

Setup Time for a Repeated START Condition

4.7

–

0.6

–

μs

T

HDDATI2C

Data Hold Time

0

–

0

–

μs

T

SUDATI2C

Data Setup Time

250

–

100

–

ns

T

SUSTOI2C

Setup Time for STOP Condition

4.0

–

0.6

–

μs

T

BUFI2C

Bus Free Time Between a STOP and START Condition

4.7

–

1.3

–

μs

T

SPI2C

Pulse Width of spikes are suppressed by the input filter.

–

–

0

50

ns