Cypress CY8C20x66 Manual De Usuario

Document Number: 001-12696  Rev. *D

Page 3 of 34

The PSoC family consists of on-chip Controller devices. These
devices are designed to replace multiple traditional MCU-based
components with one, low cost single-chip programmable
component. A PSoC device includes configurable analog and
digital blocks, and programmable interconnect. This architecture
allows the user to create customized peripheral configurations,
to match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable IO are included in a range of
convenient pinouts.

The architecture for this device family, as shown in the 

, is comprised of three main areas: the Core,

the CapSense Analog System, and the System Resources
(including a full speed USB port). A common, versatile bus allows
connection between IO and the analog system. Each
CY8C20x36/46/66, CY8C20396 PSoC device includes a
dedicated CapSense block that provides sensing and scanning
control circuitry for capacitive sensing applications. Depending
on the PSoC package, up to 36 general purpose IO (GPIO) are
also included. The GPIO provides access to the MCU and
analog mux.

The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a four-MIPS, 8-bit Harvard
architecture microprocessor.

System Resources provide additional capability, such as
configurable USB and I2C slave/SPI master-slave
communication interface, three 16-bit programmable timers, and
various system resets supported by the M8C.

The Analog System is composed of the CapSense PSoC block
and an internal 1.2V analog reference, which together support
capacitive sensing of up to 36 inputs.

The Analog System contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. Capacitive sensing is configurable on
each GPIO pin. Scanning of enabled CapSense pins are
completed quickly and easily across multiple ports. 

The Analog Mux Bus can connect to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.

Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:

■

Complex capacitive sensing interfaces, such as sliders and 
touchpads.

■

Chip-wide mux that allows analog input from any IO pin.

■

Crosspoint connection between any IO pin combinations.

When designing capacitive sensing applications, refer to the
latest signal-to-noise signal level requirements Application
Notes, which can be found under 

Documentation >> Application Notes. In general, and unless
otherwise noted in the relevant Application Notes, the minimum
signal-to-noise ratio (SNR) for CapSense applications is 5:1.

IDAC

Reference

Buffer

Vr

Cinternal

A

nal

og

 G

lobal

 B

u

s

Cap Sense Counters

Comparator

Mux

Mux

Refs

CapSense

Clock Select

Oscillator

CSCLK

IMO