Cypress CY7C1475BV33 Manual De Usuario
CY7C1471BV33
CY7C1473BV33, CY7C1475BV33
Document #: 001-15029 Rev. *B
Page 10 of 32
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are all asserted active, and (3) WE is asserted LOW.
The address presented to the address bus is loaded into the
Address Register. The Write signals are latched into the Control
Logic block. The data lines are automatically tri-stated
regardless of the state of the OE input signal. This allows the
external logic to present the data on DQs and DQP
Address Register. The Write signals are latched into the Control
Logic block. The data lines are automatically tri-stated
regardless of the state of the OE input signal. This allows the
external logic to present the data on DQs and DQP
X
.
On the next clock rise the data presented to DQs and DQP
X
(or
a subset for Byte Write operations, see section
on page 12 for details), input is latched into the
device and the write is complete. Additional accesses
(read/write/deselect) can be initiated on this cycle.
(read/write/deselect) can be initiated on this cycle.
The data written during the write operation is controlled by BW
X
signals. The CY7C1471BV33, CY7C1473BV33, and
CY7C1475BV33 provide Byte Write capability that is described
in the section
CY7C1475BV33 provide Byte Write capability that is described
in the section
on page 12. The input
WE with the selected BW
X
input selectively writes to only the
desired bytes. Bytes not selected during a Byte Write operation
remain unaltered. A synchronous self timed write mechanism is
provided to simplify the write operations. Byte write capability is
included to greatly simplify read/modify/write sequences, which
can be reduced to simple byte write operations.
remain unaltered. A synchronous self timed write mechanism is
provided to simplify the write operations. Byte write capability is
included to greatly simplify read/modify/write sequences, which
can be reduced to simple byte write operations.
Because the CY7C1471BV33, CY7C1473BV33, and
CY7C1475BV33 are common IO devices, do not drive data into
the device when the outputs are active. The Output Enable (OE)
can be deasserted HIGH before presenting data to the DQs and
DQP
CY7C1475BV33 are common IO devices, do not drive data into
the device when the outputs are active. The Output Enable (OE)
can be deasserted HIGH before presenting data to the DQs and
DQP
X
inputs. Doing so tri-states the output drivers. As a safety
precaution, DQs and DQP
X
are automatically tri-stated during
the data portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1471BV33, CY7C1473BV33, and CY7C1475BV33
have an on-chip burst counter that enables the user to supply a
single address and conduct up to four write operations without
reasserting the address inputs. ADV/LD must be driven LOW to
load the initial address, as described in section
have an on-chip burst counter that enables the user to supply a
single address and conduct up to four write operations without
reasserting the address inputs. ADV/LD must be driven LOW to
load the initial address, as described in section
on page 10. When ADV/LD is driven HIGH on the
subsequent clock rise, the Chip Enables (CE
1
, CE
2
, and CE
3
)
and WE inputs are ignored and the burst counter is incremented.
Drive the correct BW
Drive the correct BW
X
inputs in each cycle of the burst write to
write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
and the completion of the operation is not guaranteed. The
device must be deselected before entering the “sleep” mode.
CE
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
and the completion of the operation is not guaranteed. The
device must be deselected before entering the “sleep” mode.
CE
1
, CE
2
, and CE
3
, must remain inactive for the duration of
t
ZZREC
after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
I
DDZZ
Sleep mode standby current
ZZ > V
DD
– 0.2V
120
mA
t
ZZS
Device operation to ZZ
ZZ > V
DD
– 0.2V
2t
CYC
ns
t
ZZREC
ZZ recovery time
ZZ < 0.2V
2t
CYC
ns
t
ZZI
ZZ active to sleep current
This parameter is sampled
2t
CYC
ns
t
RZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
ns