Cypress CY7C64113C Manual De Usuario

Document #: 38-08001 Rev. *B

Page 20 of 51

Special care should be taken with any unused GPIO data bits. An unused GPIO data bit, either a pin on the chip or a port bit that

is not bonded on a particular package, must not be left floating when the device enters the suspend state. If a GPIO data bit is

left floating, the leakage current caused by the floating bit may violate the suspend current limitation specified by the USB

Specifications. If a ‘1’ is written to the unused data bit and the port is configured with open drain outputs, the unused data bit

remains in an indeterminate state. Therefore, if an unused port bit is programmed in open-drain mode, it must be written with a

‘0.’ Notice that the CY7C64013C part always requires that the data bits P1[7:3], P2[7,1,0], and P3[7:3] be written with a ‘0.’
In normal non-HAPI mode, reads from a GPIO port always return the present state of the voltage at the pin, independent of the

settings in the Port Data Registers. If HAPI mode is activated for a port, reads of that port return latched data as controlled by the

HAPI signals (see Section 14.0). During reset, all of the GPIO pins are set to a high-impedance input state (‘1’ in open drain

mode). Writing a ‘0’ to a GPIO pin drives the pin LOW. In this state, a ‘0’ is always read on that GPIO pin unless an external source

overdrives the internal pull-down device.

Every GPIO port can be programmed as inputs with internal pull-ups, outputs LOW or HIGH, or Hi-Z (floating, the pin is not driven

internally). In addition, the interrupt polarity for each port can be programmed. The Port Configuration bits (Figure 9-6) and the

Interrupt Enable bit (Figure 9-7 through Figure 9-10) determine the interrupt polarity of the port pins. 

As shown in Table 9-1 below, a positive polarity on an input pin represents a rising edge interrupt (LOW to HIGH), and a negative

polarity on an input pin represents a falling edge interrupt (HIGH to LOW).
The GPIO interrupt is generated when all of the following conditions are met: the Interrupt Enable bit of the associated Port

Interrupt Enable Register is enabled, the GPIO Interrupt Enable bit of the Global Interrupt Enable Register (Figure 16-1) is

enabled, the Interrupt Enable Sense (bit 2, Figure 15-1) is set, and the GPIO pin of the port sees an event matching the interrupt

polarity.
The driving state of each GPIO pin is determined by the value written to the pin’s Data Register (Figure 9-2 through Figure 9-5)

and by its associated Port Configuration bits as shown in the GPIO Configuration Register (Figure 9-6). These ports are configured

on a per-port basis, so all pins in a given port are configured together. The possible port configurations are detailed in Table 9-1.

As shown in this table below, when a GPIO port is configured with CMOS outputs, interrupts from that port are disabled.
During reset, all of the bits in the GPIO Configuration Register are written with ‘0’ to select Hi-Z mode for all GPIO ports as the

default configuration.

7

6

5

4

3

2

1

0

P3.7

P3.6

P3.5

P3.4

P3.3

P32

P3.1

P3.0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

1

1

1

1

1

1

1

1

7

6

5

4

3

2

1

0

Port 3

Config Bit 1

Port 3

Config Bit 0

Port 2

Config Bit 1

Port 2

Config Bit 0

Port 1

Config Bit 1

Port 1

Config Bit 0

Port 0 

Config Bit 1

Port 0 

Config Bit 0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0

0

0

0

0

0

0

0

1

1

0

Output LOW

0

Disabled

1

Resistive

1

– (Falling Edge)

1

0

0

Output LOW

0

Disabled

1

Output HIGH

1

Disabled

0

1

0

Output LOW

0

Disabled

1

Hi-Z

1

– (Falling Edge)

0

0

0

Output LOW

0

Disabled

1

Hi-Z

1

+ (Rising Edge)