Cypress CY7C1345G Manual De Usuario

4-Mbit (128K x 36) Flow Through Sync SRAM

•

198 Champion Court

•

San Jose

,

CA 95134-1709

•

408-943-2600

Document Number: 38-05517 Rev. *E

 Revised July 15, 2007

■

128K x 36 common IO

■

3.3V core power supply (V

DD

)

■

2.5V or 3.3V IO supply (V

DDQ

)

■

Fast clock-to-output times

❐

6.5 ns (133 MHz version)

■

Provide high performance 2-1-1-1 access rate

■

User selectable burst counter supporting Intel Pentium inter-

leaved or linear burst sequences

■

Separate processor and controller address strobes 

■

Synchronous self-timed write

■

Asynchronous output enable

■

Available in Pb-free 100-Pin TQFP package, Pb-free and 

non-Pb-free 119-Ball BGA package

■

ZZ Sleep Mode option

The CY7C1345G is a 128K x 36 synchronous cache RAM

designed to interface with high speed microprocessors with

minimum glue logic. The maximum access delay from clock rise

is 6.5 ns (133 MHz version). A two-bit on-chip counter captures

the first address in a burst and increments the address automat-

ically for the rest of the burst access. All synchronous inputs are

gated by registers controlled by a positive edge triggered Clock

Input (CLK). The synchronous inputs include all addresses, all

data inputs, address pipelining Chip Enable (CE

1

), depth

expansion Chip Enables (CE

2

 and

 

CE

3

), Burst Control inputs

(ADSC, ADSP, and ADV), Write Enables (BW

x

, and BWE), and

Global Write (GW). Asynchronous inputs include the Output

Enable (OE) and the ZZ pin.
The CY7C1345G enables either interleaved or linear burst

sequences, selected by the MODE input pin. A HIGH selects an

interleaved burst sequence, while a LOW selects a linear burst

sequence. Burst accesses are initiated with the Processor

Address Strobe (ADSP) or the cache Controller Address Strobe

(ADSC) inputs. 
Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or Address

Strobe Controller (ADSC) is active. Subsequent burst addresses

are internally generated as controlled by the Advance pin (ADV).
The CY7C1345G operates from a +3.3V core power supply

while all outputs operate with either a +2.5 or +3.3V supply. All

inputs and outputs are JEDEC standard JESD8-5 compatible.
For best practice recommendations, refer to the Cypress appli-

cation note 

.

Maximum Access Time 

6.5

8.0

ns

Maximum Operating Current 

225

205

mA

Maximum Standby Current 

40

40

mA