Cypress CY7C1339G Manual De Usuario
CY7C1339G
Document #: 38-05520 Rev. *F
Page 3 of 18
Pin Configurations
(continued)
Pin Definitions
Name
I/O
Description
A
0
, A
1
, A
Input-
Synchronous
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE
of the CLK if ADSP or ADSC is active LOW, and CE
1
,
CE
2
, and
CE
3
are sampled active. A1, A0
are fed to the two-bit counter..
BW
A
, BW
B
BW
C
, BW
D
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW
write is conducted (ALL bytes are written, regardless of the values on BW
[A:D]
and BWE).
BWE
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
asserted LOW to conduct a byte write.
CLK
Input-
Clock
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
burst counter when ADV is asserted LOW, during a burst operation.
CE
1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
CE
2
and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH. CE
1
is sampled only
when a new external address is loaded.
CE
2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
CE
1
and CE
3
to select/deselect the device.CE
2
is sampled only when a new external address is
loaded.
CE
3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
CE
1
and
CE
2
to select/deselect the device. CE
3
is sampled only when a new external address is
loaded. Not connected for BGA. Where referenced, CE
3
is assumed active throughout this
document for BGA.
OE
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
2
3
4
5
6
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/288M
NC/144M
NC
DQ
C
DQ
D
DQ
C
DQ
D
A
A
A
A
ADSP
V
DDQ
CE
2
A
DQ
C
V
DDQ
DQ
C
V
DDQ
V
DDQ
V
DDQ
DQ
D
DQ
D
NC
NC
V
DDQ
V
DD
CLK
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC/576M
NC/1G
NC
NC
NC
NC
NC
NC
NC/36M
NC/72M
NC
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
NC/9M
A
A
A
A
A
A
A0
A1
DQ
A
DQ
C
DQ
A
DQ
A
DQ
A
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
DQ
B
DQ
A
DQ
A
DQ
A
DQ
A
DQ
B
V
DD
DQ
C
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
D
DQ
D
ADSC
NC
CE
1
OE
ADV
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
MODE
NC
NC
BW
B
BW
c
NC
V
DD
NC
BW
A
NC
BWE
BW
D
ZZ
119-Ball BGA Pinout