Cypress CY8C24423A Manual De Usuario
CY8C24223A, CY8C24423A
Document Number: 3-12029 Rev. *E
Page 2 of 31
PSoC
®
Functional Overview
The PSoC
®
family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components with
one, low cost single-chip programmable device. PSoC devices
include configurable blocks of analog and digital logic, and
programmable interconnects. This architecture allows the user
to create customized peripheral configurations that match the
requirements of each individual application. Additionally, a fast
CPU, Flash program memory, SRAM data memory, and
configurable IO are included in a range of convenient pinouts and
packages.
replace multiple traditional MCU-based system components with
one, low cost single-chip programmable device. PSoC devices
include configurable blocks of analog and digital logic, and
programmable interconnects. This architecture allows the user
to create customized peripheral configurations that match the
requirements of each individual application. Additionally, a fast
CPU, Flash program memory, SRAM data memory, and
configurable IO are included in a range of convenient pinouts and
packages.
The PSoC architecture, as shown in the
page 1, is comprised of four main areas: PSoC Core, Digital
System, Analog System, and System Resources. Configurable
global busing allows all the device resources to be combined into
a complete custom system. The PSoC automotive CY8C24x23A
group can have up to three IO ports that connect to the global
digital and analog interconnects, providing access to 4 digital
blocks and 6 analog blocks.
System, Analog System, and System Resources. Configurable
global busing allows all the device resources to be combined into
a complete custom system. The PSoC automotive CY8C24x23A
group can have up to three IO ports that connect to the global
digital and analog interconnects, providing access to 4 digital
blocks and 6 analog blocks.
PSoC Core
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose IO).
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose IO).
The M8C CPU core is a powerful processor with speeds up to
12 MHz, providing a two MIPS 8-bit Harvard architecture
microprocessor. The CPU uses an interrupt controller with 11
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
12 MHz, providing a two MIPS 8-bit Harvard architecture
microprocessor. The CPU uses an interrupt controller with 11
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
Sleep and Watch Dog Timers (WDT).
Memory includes 4 KB of Flash for program storage and 256
bytes of SRAM for data storage. Program Flash uses four
protection levels on blocks of 64 bytes, allowing customized
software IP protection.
bytes of SRAM for data storage. Program Flash uses four
protection levels on blocks of 64 bytes, allowing customized
software IP protection.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator) accurate to 4%
over temperature and voltage. A low power 32 kHz ILO (internal
low speed oscillator) is provided for the Sleep timer and WDT. If
crystal accuracy is desired, the ECO (32.768 kHz external crystal
oscillator) is available for use as a Real Time Clock (RTC) and
can optionally generate a crystal-accurate 24 MHz system clock
using a PLL. The clocks, together with programmable clock
dividers (as a System Resource), provide the flexibility to
integrate almost any timing requirement into the PSoC device.
including a 24 MHz IMO (internal main oscillator) accurate to 4%
over temperature and voltage. A low power 32 kHz ILO (internal
low speed oscillator) is provided for the Sleep timer and WDT. If
crystal accuracy is desired, the ECO (32.768 kHz external crystal
oscillator) is available for use as a Real Time Clock (RTC) and
can optionally generate a crystal-accurate 24 MHz system clock
using a PLL. The clocks, together with programmable clock
dividers (as a System Resource), provide the flexibility to
integrate almost any timing requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external inter-
facing. Every pin also has the capability to generate a system
interrupt on high level, low level, and change from last read.
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external inter-
facing. Every pin also has the capability to generate a system
interrupt on high level, low level, and change from last read.
Digital System
The Digital System is composed of four digital PSoC blocks.
Each block is an 8-bit resource that can be used alone or
combined with other blocks to form 8, 16, 24, and 32-bit
peripherals, which are called user module references.
Each block is an 8-bit resource that can be used alone or
combined with other blocks to form 8, 16, 24, and 32-bit
peripherals, which are called user module references.
Figure 1. Digital System Block Diagram
Digital peripheral configurations include:
■
PWMs (8 to 32 bit)
■
PWMs with Dead Band (8 to 32 bit)
■
Counters (8 to 32 bit)
■
Timers (8 to 32 bit)
■
UART 8 bit with selectable parity
■
SPI Master and Slave
■
I2C Slave and Multi-Master (one available as a System
Resource)
Resource)
■
Cyclical Redundancy Checker/Generator (8 to 32 bit)
■
IrDA
■
Pseudo Random Sequence Generators (8 to 32 bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in the table
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in the table
DIGITAL SYSTEM
To System Bus
Digital Clocks
From Core
Digital PSoC Block Array
To Analog
System
8
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8
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Row 0
DBB00
DBB01
DCB02
DCB03
4
4
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digital
Interconnect
Port 2
Port 1
Port 0