Cypress CY7C1382D Manual De Usuario

Document #: 38-05543 Rev. *F

Page 8 of 34

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. Maximum

access delay from the clock rise (t

CO

) is 2.6 ns (250 MHz device).

The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F

supports secondary cache in systems using a linear or inter-

leaved burst sequence. The interleaved burst order supports

Pentium and i486

™ processors. The linear burst sequence suits

processors that use a linear burst sequence. The burst order is

user selectable, and is determined by sampling the MODE input.

Accesses can be initiated with either the processor address

strobe (ADSP) or the controller address strobe (ADSC). Address

advancement through the burst sequence is controlled by the

ADV input. A two-bit on-chip wraparound burst counter captures

the first address in a burst sequence and automatically incre-

ments the address for the rest of the burst access.
Byte write operations are qualified with the byte write enable

(BWE) and byte write select (BW

X

) inputs. A global write enable

(GW) overrides all byte write inputs and writes data to all four

bytes. All writes are simplified with on-chip synchronous

self-timed write circuitry.
Three synchronous chip selects (CE

1

, CE

2

, CE

3

) and an

asynchronous output enable (OE) provide for easy bank

selection and output tri-state control. ADSP is ignored if CE

1

 is

HIGH.

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,

(2) CE

1

, CE

2

, CE

3

 are all asserted active, and (3) the write

signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE

1

 is HIGH. The address presented to the address inputs (A)

is stored into the address advancement logic and the address

register while being presented to the memory array. The corre-

sponding data is enabled to propagate to the input of the output

registers. At the rising edge of the next clock, the data is enabled

to propagate through the output register and onto the data bus

within 2.6 ns (250 MHz device) if OE is active LOW. The only

exception occurs when the SRAM is emerging from a deselected

state to a selected state; its outputs are always tri-stated during

the first cycle of the access. After the first cycle of the access,

the outputs are controlled by the OE signal. Consecutive single

read cycles are supported. Once the SRAM is deselected at

clock rise by the chip select and either ADSP or ADSC signals,

its output tri-states immediately.

This access is initiated when both the following conditions are

satisfied at clock rise: (1) ADSP is asserted LOW and (2) CE

1

,

CE

2

, and CE

3

 are all asserted active. The address presented to

A is loaded into the address register and the address

advancement logic while being delivered to the memory array.

The write signals (GW, BWE, and BW

X

) and ADV inputs are

ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQs inputs is written into the corre-

sponding address location in the memory array. If GW is HIGH,

then the write operation is controlled by BWE and BW

X

 signals. 

The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F

provides byte write capability that is described in the write cycle

descriptions table. Asserting the byte write enable input (BWE)

with the selected byte write (BW

X

) input, selectively writes to only

the desired bytes. Bytes not selected during a byte write

operation remain unaltered. A synchronous self-timed write

mechanism has been provided to simplify the write operations. 
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F is a

common I/O device, the output enable (OE) must be deserted

HIGH before presenting data to the DQs inputs. Doing so

tri-states the output drivers. As a safety precaution, DQs are

automatically tri-stated whenever a write cycle is detected,

regardless of the state of OE.

ADSC write accesses are initiated when the following conditions

are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted

HIGH, (3) CE

1

, CE

2

, and CE

3

 are all asserted active, and (4) the

appropriate combination of the write inputs (GW, BWE, and

BW

X

) are asserted active to conduct a write to the desired

byte(s). ADSC-triggered Write accesses require a single clock

cycle to complete. The address presented to A is loaded into the

address register and the address advancement logic while being

delivered to the memory array. The ADV input is ignored during

this cycle. If a global write is conducted, the data presented to

the DQs is written into the corresponding address location in the

memory core. If a byte write is conducted, only the selected bytes

are written. Bytes not selected during a byte write operation

remain unaltered. A synchronous self-timed write mechanism

has been provided to simplify the write operations. 
The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F is a

common I/O device, the output enable (OE) must be deserted

HIGH before presenting data to the DQs inputs. Doing so

tri-states the output drivers. As a safety precaution, DQs are

automatically tri-stated whenever a write cycle is detected,

regardless of the state of OE.