Cypress SL811HS Manual De Usuario
SL811HS
Document 38-08008 Rev. *D
Page 21 of 32
48/28-Pin USB Host Controller Pins Description
The SL811HST-AXC is packaged in a 48-pin TQFP. The SL811HS and SL811HS-JCT packages are 28-pin PLCC’s. These
devices require a 3.3 VDC power source. The 48-Pin TQFP requires an external 12 or 48 MHz crystal or clock.
devices require a 3.3 VDC power source. The 48-Pin TQFP requires an external 12 or 48 MHz crystal or clock.
Table 35. 48/28-Pin TQFP AXC Pin Assignments and Definitions
48-Pin TQFP
AXC Pin No.
28-Pin PLCC
Pin No.
Pin Type
Pin Name
Pin Description
1
–
NC
NC
No connection.
2
–
NC
NC
No connection.
3
5
IN
nWR
Write Strobe Input. An active LOW input used with nCS to write
to registers/data memory.
to registers/data memory.
4
6
IN
nCS
Active LOW 48-Pin TQFP Chip select. Used with nRD and nWr
when accessing the 48-Pin TQFP.
when accessing the 48-Pin TQFP.
5
7
IN
CM
Clock Multiply. Select 12 MHz/48 MHz Clock Source.
6
8
VDD1
+3.3 VDC
Power for USB Transceivers. V
DD1
may be connected to V
DD
.
7
9
BIDIR
DATA +
USB Differential Data Signal HIGH Side.
8
10
BIDIR
DATA -
USB Differential Data Signal LOW Side.
9
11
GND
USB GND
Ground Connection for USB.
10
–
NC
NC
No connection.
11
–
NC
NC
No connection.
12
–
NC
NC
No connection.
13
–
NC
NC
No connection.
14
–
NC
NC
No connection.
15
12
VDD
+3.3 VDC
Device V
DD
Power.
16
13
IN
CLK/X1
Clock or External Crystal X1 connection. The X1/X2 Clock
requires external 12 or 48 MHz matching crystal or clock source.
requires external 12 or 48 MHz matching crystal or clock source.
17
14
OUT
X2
External Crystal X2 connection.
18
15
IN
nRST
Device active low reset input.
19
16
OUT
INTRQ
Active HIGH Interrupt Request output to external controller.
20
17
GND
GND
Device Ground.
21
18
BIDIR
D0
Data 0. Microprocessor Data/Address Bus.
22
–
NC
NC
No connection.
23
–
NC
NC
No connection.
24
–
NC
NC
No connection.
25
–
NC
NC
No connection.
26
–
NC
NC
No connection.
27
19
BIDIR
D1
Data 1. Microprocessor Data/Address Bus.
28
20
BIDIR
D2
Data 2. Microprocessor Data/Address Bus.
29
21
BIDIR
D3
Data 3. Microprocessor Data/Address Bus.
30
22
GND
GND
Device Ground.
31
23
BIDIR
D4
Data 4. Microprocessor Data/Address Bus.
32
24
BIDIR
D5
Data 5. Microprocessor Data/Address Bus.
Notes
5. The CM Clock Multiplier pin must be tied HIGH for a 12 MHz clock source and tied to ground for a 48 MHz clock source.
6. The CM Clock Multiplier pin must be tied HIGH for a 12 MHz clock source and tied to ground for a 48 MHz clock source. In 28-pin PLCC’s, this pin is designated
6. The CM Clock Multiplier pin must be tied HIGH for a 12 MHz clock source and tied to ground for a 48 MHz clock source. In 28-pin PLCC’s, this pin is designated
as an ALE input pin.
7. VDD can be derived from the USB supply. See Figure 5 on page 19.