Cypress SL811HS Manual De Usuario

Document 38-08008 Rev. *D

Page 28 of 32

Note nWR must go low after nDACK goes low in order for nDRQ to clear. If this sequence is not implemented as requested, the
next nDRQ is not inserted.

tdack

nDACK low

80 ns

tdwrlo

nDACK to nWR low delay

5 ns

tdakrq

nDACK low to nDRQ high delay

5 ns

 

tdwrp

nWR pulse width

65 ns

tdhld

Data hold after nWR high

5 ns

tdsu

Data set-up to nWR strobe low

 60 ns

tackrq

NDACK high to nDRQ low

5 ns

tackwrh

NDACK high to nDRQ low

5 ns

twrcycle

DMA Write Cycle Time

150 ns

          

  D A T A  

tdw rp 

tdsu 

tdack 

tdhld 

tdw rlo 

tackw rh 

tdakrq

tackrq