Cypress CY7C64013C Manual De Usuario

Document #: 38-08001 Rev. *B

Page 33 of 51

5. In master receive mode, after the master receives a byte of data: Firmware should read the data and set the ACK and 

Continue/Busy bits appropriately for the next byte. Clearing the MSTR MODE bit at the same time causes the master state 

machine to issue a stop signal to the I

2

C-compatible bus and leave the I

2

C-compatible hardware in the idle state. 

6. When the master loses arbitration: This condition clears the MSTR MODE bit and sets the ARB Lost/Restart bit immediately 

and then waits for a stop signal on the I

2

C-compatible bus to generate the interrupt. 

The Continue/Busy bit is cleared by hardware prior to interrupt conditions 1 to 4. Once the Data Register has been read or written,

firmware should configure the other control bits and set the Continue/Busy bit for subsequent transactions. Following an interrupt

from master mode, firmware should perform only one write to the Status and Control Register that sets the Continue/Busy bit,

without checking the value of the Continue/Busy bit. The Busy bit may otherwise be active and I

2

C register contents may be

changed by the hardware during the transaction, until the I

2

C interrupt occurs. 

The USB hardware consists of the logic for a full-speed USB Port. The full-speed serial interface engine (SIE) interfaces the

microcontroller to the USB bus. An external series resistor (R

ext

) must be placed in series with the D+ and D– lines, as close to

the corresponding pins as possible, to meet the USB driver requirements of the USB specifications.

The SIE allows the CY7C64x13C microcontroller to communicate with the USB host. The SIE simplifies the interface between

the microcontroller and USB by incorporating hardware that handles the following USB bus activity independently of the micro-

controller:

• Bit stuffing/unstuffing
• Checksum generation/checking
• ACK/NAK/STALL
• Token type identification
• Address checking

Firmware is required to handle the following USB interface tasks:

• Coordinate enumeration by responding to SETUP packets
• Fill and empty the FIFOs
• Suspend/Resume coordination
• Verify and select DATA toggle values

The USB device is enumerated under firmware control. The following is a brief summary of the typical enumeration process of

the CY7C64x13C by the USB host. For a detailed description of the enumeration process, refer to the USB specification. 
In this description, ‘Firmware’ refers to embedded firmware in the CY7C64x13C controller. 

1. The host computer sends a SETUP packet followed by a DATA packet to USB address 0 requesting the Device descriptor.
2. Firmware decodes the request and retrieves its Device descriptor from the program memory tables.
3. The host computer performs a control read sequence and Firmware responds by sending the Device descriptor over the USB 

bus, via the on-chip FIFOs.

4. After receiving the descriptor, the host sends a SETUP packet followed by a DATA packet to address 0 assigning a new USB 

address to the device.

5. Firmware stores the new address in its USB Device Address Register after the no-data control sequence completes.
6. The host sends a request for the Device descriptor using the new USB address.
7. Firmware decodes the request and retrieves the Device descriptor from program memory tables.
8. The host performs a control read sequence and Firmware responds by sending its Device descriptor over the USB bus.
9. The host generates control reads from the device to request the Configuration and Report descriptors.

10.Once the device receives a Set Configuration request, its functions may now be used.

USB status and control is regulated by the USB Status and Control Register, as shown in Figure 17-1. All bits in the register are

cleared during reset.