Cypress CY7C0853AV Manual De Usuario

FLEx36™ 3.3V 32K/64K/128K/256K x 36

Synchronous Dual-Port RAM

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198 Champion Court

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San Jose

,

CA 95134-1709

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408-943-2600

Document #: 38-06070 Rev. *H

 Revised July 29, 2008

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True dual-ported memory cells that allow simultaneous access 

of the same memory location

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Synchronous pipelined operation

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Organization of 1-Mbit, 2-Mbit, 4-Mbit, and 9-Mbit devices

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Pipelined output mode allows fast operation

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0.18-micron CMOS for optimum speed and power

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High-speed clock to data access 

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3.3V low power

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Active as low as 225 mA (typ)

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Standby as low as 55 mA (typ)

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Mailbox function for message passing

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Global master reset

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Separate byte enables on both ports

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Commercial and industrial temperature ranges

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IEEE 1149.1-compatible JTAG boundary scan

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172-Ball FBGA (1 mm pitch) (15 mm × 15 mm)

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176-Pin TQFP (24 mm × 24 mm × 1.4 mm)

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Counter wrap around control

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Internal mask register controls counter wrap-around

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Counter-interrupt flags to indicate wrap-around

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Memory block retransmit operation

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Counter readback on address lines

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Mask register readback on address lines

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Dual Chip Enables on both ports for easy depth expansion

The FLEx36™ family includes 1M, 2M, 4M, and 9M pipelined,

synchronous, true dual-port static RAMs that are high-speed,

low-power 3.3V CMOS. Two ports are provided, permitting

independent, simultaneous access to any location in memory.

The result of writing to the same location by more than one port

at the same time is undefined. Registers on control, address, and

data lines allow for minimal setup and hold time.
During a Read operation, data is registered for decreased cycle

time. Each port contains a burst counter on the input address

register. After externally loading the counter with the initial

address, the counter increments the address internally (more

details to follow). The internal Write pulse width is independent

of the duration of the R/W input signal. The internal Write pulse

is self-timed to allow the shortest possible cycle times. 
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down

the internal circuitry to reduce the static power consumption. One

cycle with chip enables asserted is required to reactivate the

outputs.
Additional features include: readback of burst-counter internal

address value on address lines, counter-mask registers to

control the counter wrap-around, counter interrupt (CNTINT)

flags, readback of mask register value on address lines,

retransmit functionality, interrupt flags for message passing,

JTAG for boundary scan, and asynchronous Master Reset

(MRST). 
The CY7C0853AV device in this family has limited features.

Please see 

 for details.

Part Number

CY7C0850AV

CY7C0851AV

CY7C0852AV

CY7C0853AV

Max. Speed (MHz)

167

167

167

133

Max. Access Time - Clock to Data (ns)

4.0

4.0

4.0

4.7

Typical operating current (mA)

225

225

225

270

Package

176TQFP 

172FBGA

176TQFP 

172FBGA

176TQFP 

172FBGA

172FBGA