Cypress CY7C1218H Manual De Usuario
CY7C1218H
Document #: 38-05667 Rev. *B
Page 16 of 16
Document History Page
Document Title: CY7C1218H 1-Mbit (32K x36) Pipelined Sync SRAM
Document Number: 38-05667
Document Number: 38-05667
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
343896
See ECN
PCI
New Data Sheet
*A
430678
See ECN
NXR
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Added 2.5VI/O option
Changed Three-State to Tri-State
Included Maximum Ratings for V
“3901 North First Street” to “198 Champion Court”
Added 2.5VI/O option
Changed Three-State to Tri-State
Included Maximum Ratings for V
DDQ
relative to GND
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Modified test condition from V
Electrical Characteristics Table
Modified test condition from V
IH
< V
DD
to
V
IH
< V
DD
Replaced Package Name column with Package Diagram in the Ordering
Information table
Information table
*B
481916
See ECN
VKN
Converted from Preliminary to Final.
Updated the Ordering Information table.
Updated the Ordering Information table.