Cypress CY8C21234 Manual De Usuario

Document Number: 38-12025  Rev. *O

Page 32 of 45

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V

and -40°C 

≤ T

A

 

≤ 85°C, 3.0V to 3.6V and -40°C ≤ T

A

 

≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T

A

 

≤ 85°C, respectively. Typical parameters

apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.

T

WRITE

Flash Block Write Time

–

30

–

ms

T

DSCLK

Data Out Delay from Falling Edge of SCLK

–

–

45

ns

3.6 

< Vdd

T

DSCLK3

Data Out Delay from Falling Edge of SCLK

–

–

50

ns

3.0 

≤ Vdd ≤ 3.6

T

DSCLK2

Data Out Delay from Falling Edge of SCLK

–

–

70

ns

2.4 

≤ Vdd ≤ 3.0

Table 37.  AC Programming Specifications  (continued)

≥ 3.0V

F

SCLI2C

SCL Clock Frequency

0

100

0

400

kHz

T

HDSTAI2C

Hold Time (repeated) START Condition. 

After this period, the first clock pulse is 

generated.

4.0

–

0.6

–

μs

T

LOWI2C

LOW Period of the SCL Clock

4.7

–

1.3

–

μs

T

HIGHI2C

HIGH Period of the SCL Clock

4.0

–

0.6

–

μs

T

SUSTAI2C

Set-up Time for a Repeated START 

Condition

4.7

–

0.6

–

μs

T

HDDATI2C

Data Hold Time

0

–

0

–

μs

T

SUDATI2C

Data Set-up Time

250

–

100

–

ns

T

SUSTOI2C

Set-up Time for STOP Condition

4.0

–

0.6

–

μs

T

BUFI2C

Bus Free Time Between a STOP and START 

Condition

4.7

–

1.3

–

μs

T

SPI2C

Pulse Width of spikes are suppressed by the 

input filter.

–

–

0

50

ns

21. A Fast-Mode I2C-bus device may be used in a Standard-Mode I2C-bus system, but the requirement t

SU;DAT

 

≥ 250 ns must then be met. This is automatically 

the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next 

data bit to the SDA line t

rmax

 + t

SU;DAT

 = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.