Cypress CY8C24123A Manual De Usuario

Document Number: 38-12028  Rev. *I

Page 42 of 56

The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C 

≤ T

A

 

≤ 85°C, 3.0V to 3.6V and -40°C ≤ T

A

 

≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T

A

 

≤ 85°C, respectively. Typical parameters

apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. 

T

ROB

Rising Settling Time to 0.1%, 1V Step, 100 pF Load
  Power = Low
  Power = High

–
–

–
–

4
4

μs

μs

T

SOB

Falling Settling Time to 0.1%, 1V Step, 100 pF Load
  Power = Low 
  Power = High

–
–

–
–

3
3

μs

μs

SR

ROB

Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load
  Power = Low
  Power = High

0.4
0.4

–
–

–
–

V/

μs

V/

μs

SR

FOB

Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load
  Power = Low
  Power = High

0.4
0.4

–
–

–
–

V/

μs

V/

μs

BW

OB

Small Signal Bandwidth, 20mV

pp

, 3dB BW, 100 pF Load

  Power = Low
  Power = High

0.6
0.6

–
–

–
–

MHz
MHz

BW

OB

Large Signal Bandwidth, 1V

pp

, 3dB BW, 100 pF Load

  Power = Low
  Power = High

180
180

–
–

–
–

kHz
kHz

F

OSCEXT

Frequency

0.093

–

24.6

MHz

–

High Period

20.6

–

5300

ns

–

Low Period

20.6

–

–

ns

–

Power Up IMO to Switch

150

–

–

μs

F

OSCEXT

Frequency with CPU Clock divide by 1

a

0.093

–

12.3

MHz

F

OSCEXT

Frequency with CPU Clock divide by 2 or greater

b

0.186

–

24.6

MHz

–

High Period with CPU Clock divide by 1

41.7

–

5300

ns

–

Low Period with CPU Clock divide by 1

41.7

–

–

ns

–

Power Up IMO to Switch

150

–

–

μs

a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle 

requirements.

b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the 

fifty percent duty cycle requirement is met.