Cypress CY7C107BN Manual De Usuario
CY7C107BN
CY7C1007BN
Document #: 001-06426 Rev. **
Page 3 of 7
AC Test Loads and Waveforms
Switching Characteristics
[5]
Over the Operating Range
7C107BN-15
7C1007BN-15
Parameter
Description
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
15
ns
t
AA
Address to Data Valid
15
ns
t
OHA
Data Hold from Address Change
3
ns
t
ACE
CE LOW to Data Valid
15
ns
t
LZCE
CE LOW to Low Z
[6]
3
ns
t
HZCE
CE HIGH to High Z
[6, 7]
7
ns
t
PU
CE LOW to Power-Up
0
ns
t
PD
CE HIGH to Power-Down
15
ns
WRITE CYCLE
[8]
t
WC
Write Cycle Time
15
ns
t
SCE
CE LOW to Write End
12
ns
t
AW
Address Set-Up to Write End
12
ns
t
HA
Address Hold from Write End
0
ns
t
SA
Address Set-Up to Write Start
0
ns
t
PWE
WE Pulse Width
12
ns
t
SD
Data Set-Up to Write End
8
ns
t
HD
Data Hold from Write End
0
ns
t
LZWE
WE HIGH to Low Z
[6]
3
ns
t
HZWE
WE LOW to High Z
[6, 7]
7
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZCE
and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
3.0V
5V
OUTPUT
R1 480
Ω
R2
255
Ω
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤ 3 ns
≤ 3 ns
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
1.73V
Equivalent to:
THÉ VENIN EQUIVALENT
ALL INPUT PULSES
R2
255
Ω
R1 480
Ω
167
Ω