Cypress CY7C1510KV18 Manual De Usuario

Document Number: 001-00436 Rev. *E

Page 9 of 30

Echo clocks are provided on the QDR-II to simplify data capture

on high speed systems. Two echo clocks are generated by the

QDR-II. CQ is referenced with respect to C and CQ is referenced

with respect to C. These are free running clocks and are synchro-

nized to the output clock of the QDR-II. In the single clock mode,

CQ is generated with respect to K and CQ is generated with

respect to K. The timing for the echo clocks is shown in 

These chips use a PLL that is designed to function between

120 MHz and the specified maximum clock frequency. During

power up, when the DOFF is tied HIGH, the PLL is locked after

20 

μs of stable clock. The PLL can also be reset by slowing or

stopping the input clocks K and K for a minimum of 30 ns.

However, it is not necessary to reset the PLL to lock to the

desired frequency. The PLL automatically locks 20 

μs after a

stable clock is presented. The PLL may be disabled by applying

ground to the DOFF pin. When the PLL is turned off, the device

behaves in QDR-I mode (with one cycle latency and a longer

access time).

 shows two QDR-II used in an application.

R = 250

ohms

Vt

R

R = 250

ohms

Vt

Vt

R

Vt = Vddq/2

R = 50

ohms

R

C C#

D
A

SRAM #2

R
P
S
#

W

P
S
#

B

W

S
#

ZQ

CQ/CQ#

Q

K#

C C#

D
A

K

SRAM #1

R
P
S
#

W

P
S
#

B

W

S
#

ZQ

CQ/CQ#

Q

K#

BUS

MASTER

(CPU

or

ASIC)

DATA IN

DATA OUT

Address

RPS#

WPS#
BWS#

Source K

Source K#

Delayed K

Delayed K#

CLKIN/CLKIN#

K