Cypress CY7C68034 Manual De Usuario
CY7C68033/CY7C68034
Document #: 001-04247 Rev. *D
Page 28 of 33
Slave FIFO Asynchronous Address
Figure 16. Slave FIFO Asynchronous Address Timing Diagram
Sequence Diagram
Sequence Diagram of a Single and Burst Asynchronous Read
Figure 17. Slave FIFO Asynchronous Read Sequence and Timing Diagram
Figure 18. Slave FIFO Asynchronous Read Sequence of Events Diagram
SLRD/SLWR/PKTEND
SLCS/FIFOADR [1:0]
t
SFA
t
FAH
Table 16.Slave FIFO Asynchronous Address Parameters
Parameter
Description
Min.
Max.
Unit
t
SFA
FIFOADR[1:0] to SLRD/SLWR/PKTEND Setup Time
10
ns
t
FAH
RD/WR/PKTEND to FIFOADR[1:0] Hold Time
10
ns
SLRD
FLAGS
SLOE
DATA
t
RDpwh
t
RDpwl
t
OEon
t
XFD
t
XFLG
N
Data (X)
t
XFD
N+1
t
XFD
t
OEoff
N+3
N+2
t
OEoff
t
XFLG
t
SFA
t
FAH
FIFOADR
SLCS
Driven
t
XFD
t
OEon
t
RDpwh
t
RDpwl
t
RDpwh
t
RDpwl
t
RDpwh
t
RDpwl
t
FAH
t
SFA
N
t=0
T=0
T=1
T=7
T=2
T=3
T=4
T=5
T=6
t=1
t=2
t=3
t=4
N
N
SLOE
SLRD
FIFO POINTER
N+3
FIFO DATA BUS Not Driven
Driven: X
N
Not Driven
SLOE
N
N+2
N+3
SLRD
N
N+1
SLRD
N+1
SLRD
N+1
N+2
SLRD
N+2
SLRD
N+2
N+1
SLOE
Not Driven
SLOE
N
N+1
N+1